COP87L88CF Datasheet, PDF (19/40 Pages) National Semiconductor (TI) – 8-Bit CMOS OTP Microcontrollers with 16k Memory and

A/D Converter (Continued)
sist of 1 cycle at the beginning for reset, 2 cycles for sam-
pling, 8 cycles for converting, and 1 cycle for loading the re-
sult into the A/D result register (ADRSLT). This A/D result
register is a read-only register. The device cannot write into
ADRSLT.
The prescaler also allows an A/D clock inhibit option, which
saves power by powering down the A/D when it is not in use.
Note: The A/D converter is also powered down when the device is in either
the HALT or IDLE modes. If the ADC is running when the device enters
the HALT or IDLE modes, the ADC will power down during the HALT or
IDLE, and then will reinitialize the conversion when the device comes
out of the HALT or IDLE modes.
Analog Input and Source Resistance Considerations
Figure 12 shows the A/D pin model in single ended mode.
The differential mode has similiar A/D pin model. The leads
to the analog inputs should be kept as short as possible.
Both noise and digital clock coupling to an A/D input can
cause conversion errors. The clock lead should be kept
away from the analog input line to reduce coupling. The A/D
channel input pins do not have any internal output driver cir-
cuitry connected to them because this circuitry would load
the analog input signals due to output buffer leakage current.
*The analog switch is closed only during the sample time.
FIGURE 12. A/D Pin Model (Single Ended Mode)
DS101134-28
Source impedances greater than 1 kΩ on the analog input
lines will adversely affect internal RC charging time during in-
put sampling. As shown in Figure 12, the analog switch to
the DAC array is closed only during the 2 A/D cycle sample
time. Large source impedances on the analog inputs may re-
sult in the DAC array not being charged to the correct volt-
age levels, causing scale errors.
If large source resistance is necessary, the recommended
solution is to slow down the A/D clock speed in proportion to
the source resistance. The A/D converter may be operated
at the maximum speed for R_S less than 1 kΩ. For R_S greater
than 1 kΩ, A/D clock speed needs to be reduced. For ex-
ample, with R_S = 2 kΩ, the A/D converter may be operated
at half the maximum speed. A/D converter clock speed may
be slowed down by either increasing the A/D prescaler
divide-by or decreasing the CKI clock frequency. The A/D
clock speed may be reduced to its minimum frequency of
100 kHz.
Interrupts
INTRODUCTION
Each device supports nine vectored interrupts. Interrupt
sources include Timer 0, Timer 1, Timer 2, Timer 3, Port L
Wakeup, Software Trap, MICROWIRE/PLUS, and External
Input.
All interrupts force a branch to location 00FF Hex in program
memory. The VIS instruction may be used to vector to the
appropriate service routine from location 00FF Hex.
The Software trap has the highest priority while the default
VIS has the lowest priority.
Each of the 9 maskable inputs has a fixed arbitration ranking
and vector.
Figure 13 shows the Interrupt Block Diagram.
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