COP87L88CF Datasheet, PDF (11/40 Pages) National Semiconductor (TI) – 8-Bit CMOS OTP Microcontrollers with 16k Memory and

Functional Description (Continued)
with the timers (with the exception of the IDLE timer). Data
memory is addressed directly by the instruction or indirectly
by the B, X and SP pointers.
The device has 128 bytes of RAM. Sixteen bytes of RAM are
mapped as “registers” at addresses 0F0 to 0FF Hex. These
registers can be loaded immediately, and also decremented
and tested with the DRSZ (decrement register and skip if
zero) instruction. The memory pointer registers X, SP, and B
are memory mapped into this space at address locations
0FC to 0FE Hex respectively, with the other registers (other
than reserved register 0FF) being available for general us-
age.
The instruction set permits any bit in memory to be set, reset
or tested. All I/O and registers (except A and PC) are
memory mapped; therefore, I/O bits and register bits can be
directly and individually set, reset and tested. The accumula-
tor (A) bits can also be directly and individually tested.
Note: RAM contents are undefined upon power-up.
Reset
The RESET input when pulled low initializes the microcon-
troller. Initialization will occur whenever the RESET input is
pulled low. Upon initialization, the data and configuration
registers for Ports L, G, and C are cleared, resulting in these
Ports being initialized to the TRI-STATE mode. Pin G1 of the
G Port is an exception (as noted below) since pin G1 is dedi-
cated as the WATCHDOG and/or Clock Monitor error output
pin. Port D is initialized high with RESET. The PC, PSW, CN-
TRL, ICNTRL, and T2CNTRL control registers are cleared.
The Multi-Input Wakeup registers WKEN, WKEDG, and
WKPNDare cleared. The A/D control register ENAD is
cleared, resulting in the ADC being powered down initially.
The Stack Pointer, SP, is initialized to 06F Hex.
The device comes out of reset with both the WATCHDOG
logic and the Clock Monitor detector armed, and with both
the WATCHDOG service window bits set and the Clock
Monitor bit set. The WATCHDOG and Clock Monitor detector
circuits are inhibited during reset. The WATCHDOG service
window bits are initialized to the maximum WATCHDOG ser-
vice window of 64k t_c clock cycles. The Clock Monitor bit is
initialized high, and will cause a Clock Monitor error following
reset if the clock has not reached the minimum specified fre-
quency at the termination of reset. A Clock Monitor error will
cause an active low error output on pin G1. This error output
will continue until 16–32 t_c clock cycles following the clock
frequency reaching the minimum specified value, at which
time the G1 output will enter the TRI-STATE mode.
The external RC network shown in Figure 5 should be used
to ensure that the RESET pin is held low until the power sup-
ply to the chip stabilizes.
RC > 5 x Power Supply Rise Time
DS101134-7
FIGURE 5. Recommended Reset Circuit
Oscillator Circuits
The chip can be driven by a clock input on the CKI input pin
which can be between DC and 10 MHz. The CKO output
clock is on pin G7 (crystal configuration). The CKI input fre-
quency is divided down by 10 to produce the instruction
cycle clock (1/t_c).
Figure 6 shows the Crystal and R/C diagrams.
CRYSTAL OSCILLATOR
CKI and CKO can be connected to make a closed loop crys-
tal (or resonator) controlled oscillator.
Table 1 shows the component values required for various
standard crystal values.
R/C OSCILLATOR
By selecting CKI as a single pin oscillator input, a single pin
R/C oscillator circuit can be connected to it. CKO is available
as a general purpose input, and/or HALT restart pin.
Table 2 shows the variation in the oscillator frequencies as
functions of the component (R and C) values.
DS101134-9
DS101134-8
FIGURE 6. Crystal and R/C Oscillator Diagrams
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