COP881C Datasheet, PDF (18/30 Pages) National Semiconductor (TI) – Microcontrollers

Instruction Set
REGISTER AND SYMBOL DEFINITIONS
Registers
A
8-bit Accumulator register
B
8-bit Address register
X
8-bit Address register
SP 8-bit Stack pointer register
PC 15-bit Program counter register
PU upper 7 bits of PC
PL lower 8 bits of PC
C
1-bit of PSW register for carry
HC Half Carry
GIE 1-bit of PSW register for global interrupt enable
Symbols
B Memory indirectly addressed by B register
X Memory indirectly addressed by X register
Mem Direct address memory or B
MemI Direct address memory or B or Immediate data
Imm 8-bit Immediate data
Reg Register memory addresses F0 to FF (Includes B X
and SP)
Bit Bit number (0 to 7)
w Loaded with
Exchanged with
ADD
ADC
SUBC
AND
OR
XOR
IFEQ
IFGT
IFBNE
DRSZ
SBIT
RBIT
IFBIT
X
LD A
LD mem
LD Reg
X
X
LD A
LD A
LD M
CLRA
INCA
DECA
LAID
DCORA
RRCA
SWAPA
SC
RC
IFC
IFNC
JMPL
JMP
JP
JSRL
JSR
JID
RET
RETSK
RETI
INTR
NOP
Instruction Set
add
add with carry
subtract with carry
Logical AND
Logical OR
Logical Exclusive-OR
IF equal
IF greater than
IF B not equal
Decrement Reg skip if zero
Set bit
Reset bit
If bit
Exchange A with memory
Load A with memory
Load Direct memory Immed
Load Register memory Immed
Exchange A with memory B
Exchange A with memory X
Load A with memory B
Load A with memory X
Load Memory Immediate
Clear A
Increment A
Decrement A
Load A indirect from ROM
DECIMAL CORRECT A
ROTATE A RIGHT THRU C
Swap nibbles of A
Set C
Reset C
If C
If not C
Jump absolute long
Jump absolute
Jump relative short
Jump subroutine long
Jump subroutine
Jump indirect
Return from subroutine
Return and Skip
Return from Interrupt
Generate an interrupt
No operation
w A A a MemI
w w A A a MemI a C C Carry
w HC Half Carry
w w A A a MemI aC C Carry
w HC Half Carry
w A A and MemI
w A A or MemI
w A A xor MemI
Compare A and MemI Do next if A e MemI
Compare A and MemI Do next if A l MemI
Do next if lower 4 bits of B i Imm
w Reg Reg b 1 skip if Reg goes to 0
1 to bit
Mem (bite 0 to 7 immediate)
0 to bit
Mem
If bit
Mem is true do next instr
A
Mem
A w MemI
Mem w Imm
Reg w Imm
A
w B (B Bg1)
A
w X (X Xg1)
A w B w (B Bg1)
A w X w (X Xg1)
B w Imm (B w Bg1)
Aw0
AwAa1
AwAb1
w A ROM(PU A)
w A BCD correction (follows ADC SUBC)
C x A7 x x A0 x C
A7 A4
A3 A0
C w 1 HC w 1
C w 0 HC w 0
If C is true do next instruction
If C is not true do next instruction
w PC ii (ii e 15 bits 0 to 32k)
w PC11 0 i (i e 12 bits)
w PC PC a r (r is b31 to a32 not 1)
SP w PL SP-1 w PU SP-2 PC w ii
SP w PL SP-1 w PU SP-2 PC11 0 w i
w PL ROM(PU A)
SPa2 PL w SP PU w SP-1
w w SPa2 PL
SP PU
SP-1 Skip next instruction
SPa2 PL w SP PU w SP-1 GIE w 1
SP w PL SPb1 w PU SP-2 PC w 0FF
PC w PC a 1
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