COP881C Datasheet, PDF (13/30 Pages) National Semiconductor (TI) – Microcontrollers

Functional Description (Continued)
The device has three mask options for configuring the clock
input The CKI and CKO pins are automatically configured
upon selecting a particular option
Crystal (CKI 10) CKO for crystal configuration
External (CKI 10) CKO available as G7 input
R C (CKI 10) CKO available as G7 input
G7 can be used either as a general purpose input or as a
control input to continue from the HALT mode
HALT MODE
The device supports a power saving mode of operation
HALT The controller is placed in the HALT mode by setting
the G7 data bit alternatively the user can stop the clock
input In the HALT mode all internal processor activities in-
cluding the clock oscillator are stopped The fully static ar-
chitecture freezes the state of the controller and retains all
information until continuing In the HALT mode power re-
quirements are minimal as it draws only leakage currents
and output current The applied voltage (V_CC) may be de-
creased down to Vr (minimum RAM retention voltage) with-
out altering the state of the machine
There are two ways to exit the HALT mode via the RESET
or by the CKO pin A low on the RESET line reinitializes the
microcontroller and starts executing from the address
0000H A low to high transition on the CKO pin (only if the
external or R C clock option selected) causes the micro-
controller to continue with no reinitialization from the ad-
dress following the HALT instruction This also resets the
G7 data bit
INTERRUPTS
There are three interrupt sources as shown below
A maskable interrupt on external G0 input (positive or nega-
tive edge sensitive under software control)
A maskable interrupt on timer underflow or timer capture
A non-maskable software error interrupt on opcode zero
INTERRUPT CONTROL
The GIE (global interrupt enable) bit enables the interrupt
function This is used in conjunction with ENI and ENTI to
select one or both of the interrupt sources This bit is reset
when interrupt is acknowledged
ENI and ENTI bits select external and timer interrupt re-
spectively Thus the user can select either or both sources
to interrupt the microcontroller when GIE is enabled
IEDG selects the external interrupt edge (0 e rising edge
1 e falling edge) The user can get an interrupt on both
rising and falling edges by toggling the state of IEDG bit
after each interrupt
IPND and TPND bits signal which interrupt is pending After
interrupt is acknowledged the user can check these two
bits to determine which interrupt is pending This permits the
interrupts to be prioritized under software The pending flags
have to be cleared by the user Setting the GIE bit high
inside the interrupt subroutine allows nested interrupts
The software interrupt does not reset the GIE bit This
means that the controller can be interrupted by other inter-
rupt sources while servicing the software interrupt
INTERRUPT PROCESSING
The interrupt once acknowledged pushes the program
counter (PC) onto the stack and the stack pointer (SP) is
decremented twice The Global Interrupt Enable (GIE) bit is
reset to disable further interrupts The microcontroller then
vectors to the address 00FFH and resumes execution from
that address This process takes 7 cycles to complete At
the end of the interrupt subroutine any of the following
three instructions return the processor back to the main pro-
gram RET RETSK or RETI Either one of the three instruc-
tions will pop the stack into the program counter (PC) The
stack pointer is then incremented twice The RETI instruc-
tion additionally sets the GIE bit to re-enable further inter-
rupts
Any of the three instructions can be used to return from a
hardware interrupt subroutine The RETSK instruction
should be used when returning from a software interrupt
subroutine to avoid entering an infinite loop
Note There is always the possibility of an interrupt occurring during an in-
struction which is attempting to reset the GIE bit or any other interrupt
enable bit If this occurs when a single cycle instruction is being used
to reset the interrupt enable bit the interrupt enable bit will be reset
but an interrupt may still occur This is because interrupt processing is
started at the same time as the interrupt bit is being reset To avoid
this scenario the user should always use a two three or four cycle
instruction to reset interrupt enable bits
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