DS99R101 Datasheet, PDF (17/24 Pages) National Semiconductor (TI) – 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

must monitor the LOCK pin to determine whether data on the
ROUT is valid.
POWERDOWN
The Powerdown state is a low power sleep mode that the Se-
rializer and Deserializer may use to reduce power when no
data is being transferred. The TPWDNB and RPWDNB are
used to set each device into power down mode, which re-
duces supply current to the µA range. The Serializer enters
powerdown when the TPWDNB pin is driven low. In power-
down, the PLL stops and the outputs go into TRI-STATE,
disabling load current and reducing supply. To exit Power-
down, TPWDNB must be driven high. When the Serializer
exits Powerdown, its PLL must lock to TCLK before it is ready
for the Initialization state. The system must then allow time for
Initialization before data transfer can begin. The Deserializer
enters powerdown mode when RPWDNB is driven low. In
powerdown mode, the PLL stops and the outputs enter TRI-
STATE. To bring the Deserializer block out of the powerdown
state, the system drives RPWDNB high.
Both the Serializer and Deserializer must reinitialize and re-
lock before data can be transferred. The Deserializer will
initialize and assert LOCK high when it is locked to the en-
coded clock.
TRI-STATE
For the Serializer, TRI-STATE is entered when the DEN or
TPWDNB pin is driven low. This will TRI-STATE both driver
output pins (DOUT+ and DOUT−). When DEN is driven high,
the serializer will return to the previous state as long as all
other control pins remain static (TPWDNB, TRFB).
When you drive the REN or RPWDNB pin low, the Deserial-
izer enters TRI-STATE. Consequently, the receiver output
pins (ROUT0–ROUT23) and RCLK will enter TRI-STATE.
The LOCK output remains active, reflecting the state of the
PLL. The Deserializer input pins are high impedance during
receiver powerdown (RPWDNB low) and power-off (V_DD =
0V).
AC-COUPLING AND TERMINATION
The DS99R101 and DS99R102 supports AC-coupled inter-
connects through integrated DC balanced encoding/decoding
scheme. To use AC coupled connection between the Serial-
izer and Deserializer, insert external AC coupling capacitors
in series in the LVDS signal path as illustrated in . The Dese-
rializer input stage is designed for AC-coupling by providing
a built-in AC bias network which sets the internal V_CM to
+1.2V. With AC signal coupling, capacitors provide the ac-
coupling path to the signal input.
For the high-speed LVDS transmissions, the smallest avail-
able package should be used for the AC coupling capacitor.
This will help minimize degradation of signal quality due to
package parasitics. The most common used capacitor value
for the interface is 100 nF (0.1 uF) capacitor.
A termination resistor across DOUT± is also required for
proper operation to be obtained. The termination resistor
should be equal to the differential impedance of the media
being driven. This should be in the range of 90 to 132 Ohms.
100 Ohms is a typical value common used with standard 100
Ohm transmission media. This resistor is required for control
of reflections and also to complete the current loop. It should
be placed as close to the Serializer DOUT± outputs to mini-
mize the stub length from the pins. To match with the defer-
ential impedance on the transmission line, the LVDS I/O are
terminated with 100 ohm resistors on Serializer DOUT± out-
puts pins.
PROGRESSIVE TURN–ON (PTO)
Deserializer ROUT[23:0] outputs are grouped into three
groups of eight, with each group switching about 0.5UI apart
in phase to reduce EMI, simultaneous switching noise, and
system ground bounce.
Applications Information
USING THE DS99R101 AND DS99R102
The
DS99R101/DS99R102
Serializer/Deserializer
(SERDES) pair sends 24 bits of parallel LVCMOS data over
a serial LVDS link up to 960 Mbps. Serialization of the input
data is accomplished using an on-board PLL at the Serializer
which embeds clock with the data. The Deserializer extracts
the clock/control information from the incoming data stream
and deserializes the data. The Deserializer monitors the in-
coming clockl information to determine lock status and will
indicate lock by asserting the LOCK output high.
POWER CONSIDERATIONS
An all CMOS design of the Serializer and Deserializer makes
them inherently low power devices. Additionally, the constant
current source nature of the LVDS outputs minimize the slope
of the speed vs. I_DD curve of CMOS designs.
NOISE MARGIN
The Deserializer noise margin is the amount of input jitter
(phase noise) that the Deserializer can tolerate and still reli-
ably recover data. Various environmental and systematic fac-
tors include:
Serializer: TCLK jitter, V_DD noise (noise bandwidth and out-
of-band noise)
Media: ISI, V_CM noise
Deserializer: V_DD noise
For a graphical representation of noise margin, please see
Figure 16.
TRANSMISSION MEDIA
The Serializer and Deserializer can be used in point-to-point
configuration, through a PCB trace, or through twisted pair
cable. In a point-to-point configuration, the transmission me-
dia needs be terminated at both ends of the transmitter and
receiver pair. Interconnect for LVDS typically has a differential
impedance of 100 Ohms. Use cables and connectors that
have matched differential impedance to minimize impedance
discontinuities. In most applications that involve cables, the
transmission distance will be determined on data rates in-
volved, acceptable bit error rate and transmission medium.
LIVE LINK INSERTION
The Serializer and Deserializer devices support live plug-
gable applications. The “Hot Inserted” operation on the serial
interface does not disrupt communication data on the active
data lines. The automatic receiver lock to random data “plug
& go” live insertion capability allows the DS99R102 to attain
lock to the active data stream during a live insertion event.
PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS
Circuit board layout and stack-up for the LVDS SERDES de-
vices should be designed to provide low-noise power feed to
the device. Good layout practice will also separate high fre-
quency or high-level inputs and outputs to minimize unwanted
stray noise pickup, feedback and interference. Power system
performance may be greatly improved by using thin di-
electrics (2 to 4 mils) for power / ground sandwiches. This
arrangement provides plane capacitance for the PCB power
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