DS99R101 Datasheet, PDF (10/24 Pages) National Semiconductor (TI) – 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

Note: C_L includes instrumentation and fixture capacitance within 6 cm of ROUT[23:0]
FIGURE 13. Deserializer TRI-STATE Test Circuit and Timing
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FIGURE 14. Deserializer PLL Lock Times and RPWDNB TRI-STATE Delay
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