LP3941A Datasheet, PDF (15/32 Pages) National Semiconductor (TI) – Cellular Phone Power Management Unit

I²C Compatible Interface Electrical Characteristics (Continued)
P = (T_J – T_A)/θ_JA,
(1)
where T_J is the junction temperature, T_A is the ambient temperature, and θ_JA is the junction-to-ambient thermal resistance.
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care
must be paid to thermal dissipation issues in board design.
Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T_J = 150^oC (typ.) and disengages at T_J = 140^oC
(typ.).
Note 4: For detailed soldering specifications and information, please refer to National Semiconductor Application Note 1187: Leadless Leadframe Package (LLP)
(AN-1187).
Note 5: The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. (MIL-STD-883 3015.7) The machine model is a 200 pF
capacitor discharged directly into each pin. (EAIJ)
Note 6: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be
derated. Maximum ambient temperature (T_A-MAX) is dependent on the maximum operating junction temperature (T_J-MAX-OP = 125˚C), the maximum power
dissipation of the device in the application (P_D-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θ_JA), as given by the
following equation: T_A-MAX = T_J-MAX-OP − (θ_JA x P_D-MAX).
Note 7: Junction-to-ambient thermal resistance (θ_JA) is taken from a thermal modeling result, performed under the conditions and guidelines set forth in the JEDEC
standard JESD51–7. The test board is a 4-layer FR-4 board measuring 102 mm x 76 mm x 1.6 mm with a 2x1 array of thermal vias. The ground plane on the board
is 50 mm x 50 mm. Thickness of copper layers are 36 µm/1.8 µm/18 µm/36 µm (1.5 oz/1 oz/1 oz/1.5 oz). Ambient temperature in simulation is 22˚C, still air. Power
dissipation is 1W.
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care
must be paid to thermal dissipation issues in board design.
The value of θ_JA of this product can vary significantly, depending on PCB material, layout, and environmental conditions. In applications where high maximum power
dissipation exists (high V_IN, high I_OUT), special care must be paid to thermal dissipation issues. For more information on these topics, please refer to Application Note
1187: Leadless Leadframe Package (LLP) and the Power Efficiency and Power Dissipation section of this datasheet.
Note 8: All limits are guaranteed by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested during production
with T_J = 25˚C. All hot and cold limits are guaranteed by correlating the electrical characteristics to process and temperature variations and applying statistical
process control.
Note 9: Capacitors: Low-ESR Surface-Mount Ceramic Capacitors are (MLCCs) used in setting electrical characteristics.
Note 10: Guaranteed by design.
Note 11: Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This specification does not apply
in cases it implies operation with an input voltage below the 3.0V minimum appearing under Operating Ratings. For example, this specification does not apply for
devices having 1.5V outputs because the specification would imply operation with an input voltage at or about 1.5V.
Note 12: LP3941A is not intended as a Li-Ion battery protection device. Battery used in this application should have an adequate internal protection.
15
www.national.com