LP3927 Datasheet, PDF (13/16 Pages) National Semiconductor (TI) – Cellular/PCS System Power Management IC

VEXT Detect W/Keyboard Interrupts
Note: Diagram indicates Open Drain IRQ tied to V_DD.
*** = Internal signal
1. VEXT goes active low.
2. VEXT 32 msec de-bounce period.
3. Delay between LDO1 and LDO2 enable.
4. Both LDO1 and LDO2 outputs reach 95% of respective output voltage, start Reset timer.
5. Reset delay.
6. Keyboard de-bounce delay.
7. Keyboard pulse must be a minimum of 32 msec.
8. PS_HOLD may go low after Key press, but LDOs stay on since VEXT is low.
9. VEXT goes high, begin shutdown since PS_HOLD is low.
10. Delay between RST going low and LDO2 disabled.
11. Delay between LDO2 disable and LDO1 disabled.
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