LMH6582_0708 Datasheet, PDF (13/16 Pages) National Semiconductor (TI) – 16x8 550MHz Analog Crosspoint Switch, Gain of 1

Serial programming mode is the mode selected by bringing
the MODE pin low. In this mode a stream of 40 bits programs
all 8 outputs of the crosspoint. The data is fed to the chip as
shown in the table above. The table is arranged such that the
first bit clocked into the crosspoint register is labeled bit num-
ber 0. The register labeled Load Register in the block diagram
is a shift register. If the chip select pin is left low after the valid
data is shifted into the chip and if the clock signal keeps run-
ning then additional data will be shifted into the register, and
the desired data will be shifted out.
Timing Diagram
Addressed programming mode makes it possible to change
only one output register at a time. To utilize this mode the
mode pin must be High. All other pins function the same as
in serial programming mode except that the word clocked in
is 8 bits and is directed only at the output specified. In ad-
dressed mode the data format is shown below in the table
titled Addressed Mode Word Format General Case.
Addressed Mode Timing Diagram
20214410
Addressed Mode Word Format General Case
Output Address
LSB
MSB
Input Address
LSB
0
1
2
3
4
Bit 0 is first bit clocked into device.
DAISY CHAIN OPTION IN SERIAL MODE
The LMH6582 supports daisy chaining of the serial data
stream between multiple chips. This feature is available only
in the Serial programming mode. To use this feature serial
data is clocked into the first chip DIN pin, and the next chip
DIN pin is connected to the D_OUT pin of the first chip. Both
chips may share a chip select signal, or the second chip can
be enabled separately. When the chip select pin goes low on
both chips a double length word is clocked into the first chip.
As the first word is clocking into the first chip the second chip
is receiving the data that was originally in the shift register of
the first chip. When a full 40 bits have been clocked into the
first chip the next clock cycle begins moving the first frame of
the new configuration data into the second chip. With a full 80
clock cycles both chips have valid data and the chip select pin
of both chips should be brought high to prevent the data from
overshooting. A configure pulse will activate the new config-
uration on both chips simultaneously, or each chip can be
configured separately. The mode, chip select, configure and
TRI-STATE
MSB
1 = TRI-STATE
0 = On
5
6
7
clock pins of both chips can be tied together and driven from
the same sources.
SPECIAL CONTROL PINS
The LMH6582 has two special control pins that function in-
dependent of the serial control bus. One of these pins is the
reset (RST) pin. The RST pin is active high meaning that a
logic 1 level the chip is configured with all outputs disabled
and in a high impedance state. The RST pin programs all the
registers with input address 0 and all the outputs are turned
off. In this configuration the device draws only 20 mA. The
reset pin can used as a shutdown function to reduce power
consumption. The other special control pin is the broadcast
(BCST) pin. The BCST pin is also active high and sets all the
outputs to the on state connected to input 0. This is sometimes
referred to as broadcast mode, where input 0 is broadcast to
all 8 outputs.
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