LMH6582_0708 Datasheet, PDF (11/16 Pages) National Semiconductor (TI) – 16x8 550MHz Analog Crosspoint Switch, Gain of 1

FIGURE 6. Buffered Output
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In this example R_OUT is to improve settling time by isolating
the LMH6703 input capacitance from the crosspoint output.
The resistor R_L is optional. It may improve performance by
providing a small DC load for the LMH6582 output stage.
CROSSTALK
When designing a large system such as a video router
crosstalk can be a very serious problem. Extensive testing in
our lab has shown that most crosstalk is related to board lay-
out rather than occurring in the crosspoint switch. There are
many ways to reduce board related crosstalk. Using con-
trolled impedance lines is an important step. Using well de-
coupled power and ground planes will help as well. When
crosstalk does occur within the crosspoint switch it self it is
often due to signals coupling into the power supply pins. Using
appropriate supply bypassing will help to reduce this mode of
coupling. Another suggestion is to place as much grounded
copper as possible between input and output signal traces.
Care must be taken, though, not to influence the signal trace
impedances by placing shielding copper too closely. One oth-
er caveat to consider is that as shielding materials come
closer to the signal trace the trace needs to be smaller to keep
the impedance from falling too low. Using thin signal traces
will result in unacceptable losses due to resistive losses. This
effect becomes even more pronounced at higher frequencies
due to the skin effect. The skin effect reduces the effective
thickness of the trace as frequency increases. Resistive loss-
es make crosstalk worse because as the desired signal is
attenuated with higher frequencies crosstalk increases at
higher frequencies.
DIGITAL CONTROL
Block Diagram
FIGURE 7.
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The LMH6582 has internal control registers that store the
programming states of the crosspoint switch. The logic is two
staged to allow for maximum programming flexibility. The first
stage of the control logic is tied directly to the crosspoint
switching matrix. This logic consists of one register for each
output that stores the on/off state and the address of which
input to connect to. These registers are not directly accessible
by the user. The second level of logic is another bank of reg-
isters identical to the first, but set up as shift registers. These
registers are accessed by the user via the serial input bus. As
described further below, there are two modes for programing
the LMH6582, Serial Mode and Addressed Mode.
The LMH6582 is programmed via a serial input bus with the
support of 4 other digital control pins. The Serial bus consists
of a clock pin (CLK), a serial data in pin (DIN), and a serial
data out pin (D_OUT). The serial bus is gated by a chip select
pin (CS). The chip select pin is active low. While the chip se-
lect pin is high all data on the serial input pin and clock pins
is ignored. When the chip select pin is brought low the internal
logic is set to begin receiving data by the first positive transi-
tion (0 to 1) of the clock signal. The chip select pin must be
brought low at least 5 ns before the first rising edge of the
clock signal. The first data bit is clocked in on the next nega-
tive transition (1 to 0). All input data is read from the bus on
the negative edge of the clock signal. Once the last valid data
has been clocked in, the chip select pin must go high and then
the clock signal must make at least one low to high transition.
Otherwise invalid data will be clocked into the chip. The data
clocked into the chip is not transferred to the crosspoint matrix
until the CFG pin is pulsed high. This is the case regardless
of the state of the Mode pin. The CFG pin is not dependent
on the state of the Chip select pin. If no new data is clocked
into the chip subsequent pulses on the CFG pin will have no
effect on device operation.
There are two ways to connect the serial data pins. The first
way is to control all 4 pins separately, and the second option
is to connect the CFG and the CS pins together for a 3 wire
interface. The benefit of the 4 wire interface is that the chip
can be configured independently of the CS pin. This would be
an advantage in a system with multiple crosspoint chips
where all of them could be programmed ahead of time and
then configured simultaneously. The 4 wire solution is also
helpful in a system that has a free running clock on the CLK
pin. In this case, the CS pin needs to be brought high after the
last valid data bit to prevent invalid data from being clocked
into the chip.
The three wire option provides the advantage of one less pin
to control at the expense of having less flexibility with the
configure pin. One way around this loss of flexibility would be
If the clock signal is generated by an FPGA or microcontroller
where the clock signal can be stopped after the data is
clocked in. In this case the Chip select function is provided by
the presence or absence of the clock signal.
The programming format of the incoming serial data is se-
lected by the MODE pin. When the mode pin is HIGH the
crosspoint can be programmed one output at a time by en-
tering a string of data that contains the address of the output
that is going to be changed (Addressed Mode). When the
mode pin is LOW the crosspoint is in Serial Mode. In this
mode the crosspoint accepts a 40 bit array of data that pro-
grams all of the outputs. In both modes the data fed into the
chip does not change the chip operation until the Configure
pin is pulsed high. The configure and mode pins are inde-
pendent of the chip select pin.
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