DS90CR217 Datasheet, PDF (13/15 Pages) National Semiconductor (TI) – +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 75 MHz

Applications Information (Continued)
characteristic impedance (90Ω to 120Ω typical) of the cable.
Figure 18 shows an example. No additional pull-up or pull-
down resistors are necessary as with some other differential
technologies such as PECL. Surface mount resistors are
recommended to avoid the additional inductance that ac-
companies leaded resistors. These resistors should be
placed as close as possible to the receiver input pins to re-
duce stubs and effectively terminate the differential lines.
FIGURE 18. LVDS Serialized Link Termination
DS100871-24
DECOUPLING CAPACITORS: Bypassing capacitors are
needed to reduce the impact of switching noise which could
limit performance. For a conservative approach three
parallel-connected decoupling capacitors (Multi-Layered Ce-
ramic type in surface mount form factor) between each V_CC
and the ground plane(s) are recommended. The three ca-
pacitor values are 0.1 µF, 0.01µF and 0.001 µF. An example
is shown in Figure 19. The designer should employ wide
traces for power and ground and ensure each capacitor has
its own via to the ground plane. If board space is limiting the
number of bypass capacitors, the PLL V_CC should receive
the most filtering/bypassing. Next would be the LVDS V_CC
pins and finally the logic V_CC pins.
DS100871-25
FIGURE 19. CHANNEL LINK
Decoupling Configuration
CLOCK JITTER: The CHANNEL LINK devices employ a
PLL to generate and recover the clock transmitted across the
LVDS interface. The width of each bit in the serialized LVDS
data stream is one-seventh the clock period. For example, a
75 MHz clock has a period of 13.33 ns which results in a
data bit width of 1.90 ns. Differential skew (∆t within one dif-
ferential pair), interconnect skew (∆t of one differential pair to
another) and clock jitter will all reduce the available window
for sampling the LVDS serial data streams. Care must be
taken to ensure that the clock input to the transmitter be a
clean low noise signal. Individual bypassing of each V_CC to
ground will minimize the noise passed on to the PLL, thus
creating a low jitter LVDS clock. These measures provide
more margin for channel-to-channel skew and interconnect
skew as a part of the overall jitter/skew budget.
COMMON MODE vs. DIFFERENTIAL MODE NOISE MAR-
GIN: The typical signal swing for LVDS is 300 mV centered
at +1.2V. The CHANNEL LINK receiver supports a 100 mV
threshold therefore providing approximately 200 mV of differ-
ential noise margin. Common mode protection is of more im-
portance to the system’s operation due to the differential
data transmission. LVDS supports an input voltage range of
Ground to +2.4V. This allows for a ±1.0V shifting of the cen-
ter point due to ground potential differences and common
mode noise.
POWER SEQUENCING AND POWERDOWN MODE: Out-
puts of the CNANNEL LINK transmitter remain in TRI-STATE
until the power supply reaches 2V. Clock and data outputs
will begin to toggle 10 ms after V_CC has reached 3V and the
Powerdown pin is above 1.5V. Either device may be placed
into a powerdown mode at any time by asserting the Power-
down pin (active low). Total power dissipation for each de-
vice will decrease to 5 µW (typical).
The CHANNEL LINK chipset is designed to protect itself
from accidental loss of power to either the transmitter or re-
ceiver. If power to the transmit board is lost, the receiver
clocks (input and output) stop. The data outputs (RxOUT) re-
tain the states they were in when the clocks stopped. When
the receiver board loses power, the receiver inputs are
shorted to V _CC through an internal diode. Current is limited
(5 mA per input) by the fixed current mode drivers, thus
avoiding the potential for latchup when powering the device.
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