DS90CR217 Datasheet, PDF (1/15 Pages) National Semiconductor (TI) – +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 75 MHz

November 1999
DS90CR217/DS90CR218
+3.3V Rising Edge Data Strobe LVDS 21-Bit Channel
Link - 75 MHz
General Description
The DS90CR217 transmitter converts 21 bits of CMOS/TTL
data into three LVDS (Low Voltage Differential Signaling)
data streams. A phase-locked transmit clock is transmitted in
parallel with the data streams over a fourth LVDS link. Every
cycle of the transmit clock 21 bits of input data are sampled
and transmitted. The DS90CR218 receiver converts the
three LVDS data streams back into 21 bits of CMOS/TTL
data. At a transmit clock frequency of 75 MHz, 21 bits of TTL
data are transmitted at a rate of 525 Mbps per LVDS data
channel. Using a 75 MHz clock, the data throughput is 1.575
Gbit/s (197 Mbytes/sec).
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
Features
n 20 to 75 MHz shift clock support
n 50% duty cycle on receiver output clock
n Best–in–Class Set & Hold Times on TxINPUTs and
RxOUTPUTs
n Low power consumption
n Tx + Rx Power-down mode <400µW (max)
n ±1V common mode range (around +1.2V)
n Narrow bus reduces cable size and cost
n Up to 1.575 Gbps throughput
n Up to 197 Megabytes/sec bandwidth
n 345 mV (typ) swing LVDS devices for low EMI
n PLL requires no external components
n Rising edge data strobe
n Compatible with TIA/EIA-644 LVDS standard
n Low profile 48-lead TSSOP package
Block Diagrams
DS90CR217
DS90CR218
Order Number DS90CR217MTD
See NS Package Number MTD48
DS100871-1
Order Number DS90CR218MTD
See NS Package Number MTD48
DS100871-27
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© 1999 National Semiconductor Corporation DS100871
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