LMC6462_14 Datasheet, PDF (12/32 Pages) National Semiconductor (TI) – LMC6462 Dual/LMC6464 Quad Micropower, Rail-to-Rail Input and Output CMOS

LMC6462, LMC6464
SNOS725D – MAY 1999 – REVISED MARCH 2013
www.ti.com
Figure 34. A ±7.5V Input Signal Greatly Exceeds the 3V Supply in Figure 35 Causing No Phase Inversion
Due to R_I
Figure 35. Input Current Protection for Voltages Exceeding the Supply Voltage
Rail-to-Rail Output
The approximated output resistance of the LMC6462/4 is 180Ω sourcing, and 130Ω sinking at V_S = 3V, and
110Ω sourcing and 83Ω sinking at V_S = 5V. The maximum output swing can be estimated as a function of load
using the calculated output resistance.
Capacitive Load Tolerance
The LMC6462/4 can typically drive a 200 pF load with V_S = 5V at unity gain without oscillating. The unity gain
follower is the most sensitive configuration to capacitive load. Direct capacitive loading reduces the phase margin
of op-amps. The combination of the op-amp's output impedance and the capacitive load induces phase lag. This
results in either an underdamped pulse response or oscillation.
Capacitive load compensation can be accomplished using resistive isolation as shown in Figure 36. If there is a
resistive component of the load in parallel to the capacitive component, the isolation resistor and the resistive
load create a voltage divider at the output. This introduces a DC error at the output.
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