DS92LV1023E Datasheet, PDF (12/13 Pages) National Semiconductor (TI) – 30-66 MHz 10 Bit Bus LVDS Serializer

Pin Diagram
DS92LV1023EMQ - Serializer
Serializer Pin Description
Pin Name
I/O
DIN
I
No.
3–12
TCLK_R/F
I
13
DO+
DO−
DEN
PWRDN
O
22
O
21
I
19
I
24
TCLK
SYNC
I
14
I
1, 2
DVCC
DGND
AVCC
AGND
I
27, 28
I
15, 16
I
17, 26
I
18, 25, 20, 23
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Description
Data Input. LVTTL levels inputs. Data on these pins are loaded into
a 10-bit input register.
Transmit Clock Rising/Falling strobe select. LVTTL level input.
Selects TCLK active edge for strobing of DIN data. High selects
rising edge. Low selects falling edge.
+ Serial Data Output. Non-inverting Bus LVDS differential output.
− Serial Data Output. Inverting Bus LVDS differential output.
Serial Data Output Enable. LVTTL level input. A low, puts the Bus
LVDS outputs in TRI-STATE.
Powerdown. LVTTL level input. PWRDN driven low shuts down the
PLL and TRI-STATEs outputs putting the device into a low power
sleep mode.
Transmit Clock. LVTTL level input. Input for 40 MHz–66 MHz
(nominal) system clock.
Assertion of SYNC (high) for at least 1024 synchronization symbols
to be transmitted on the Bus LVDS serial output. Synchronization
symbols continue to be sent if SYNC continues asserted. TTL level
input. The two SYNC pins are ORed.
Digital Circuit power supply.
Digital Circuit ground.
Analog power supply (PLL and Analog Circuits).
Analog ground (PLL and Analog Circuits).
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