DS92LV1023E Datasheet, PDF (10/13 Pages) National Semiconductor (TI) – 30-66 MHz 10 Bit Bus LVDS Serializer

AC Timing Diagrams and Test Circuits (Continued)
SW - Setup and Hold Time (Internal Data Sampling Window)
t_DJIT - Serializer Output Bit Position Jitter that results from Jitter on TCLK
t_RNM = Receiver Noise Margin Time
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FIGURE 10. Receiver Bus LVDS Input Skew Margin
V_OD = (DO⁺)–(DO^−).
Differential output signal is shown as (DO+)–(DO−), device in Data Transfer mode.
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FIGURE 11. V_OD Diagram
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