LM363 Datasheet, PDF (11/22 Pages) National Semiconductor (TI) – LM363 Precision Instrumentation Amplifier

Application Hints (Continued)
Because the LM363’s offset voltage is so low to begin with
offset nulling has a negligible effect on offset temperature
drift For example zeroing a 100 mV offset assuming external
resistor TC of 200 ppm C and worst-case internal resistor
TC results in an additional drift component of 0 08 mV C
For this reason drift specifications are guaranteed with or
without external offset nulling
GAIN ADJUSTMENT
Gain may be increased by adding an external voltage divid-
er between output force and sense and reference the pre-
ferred connection is shown in Figure 4 Since both the
sense and reference pins look like 50 kX (g20 kX) to V^b
impedances presented to both pins must be equal to avoid
offset error For example a 100X imbalance can create a
worst-case output offset of 50 mV creating an input-re-
ferred error of 5 mV at Ge10 or 50 mV at Ge1000
Increasing gain this way increases output offset error An
LM363H-100 may have an output offset of 5 mV resulting in
input referred offset component of 50 mV Raising the gain
to 200 yields a 10 mV error at the output and changes input
referred error by an additional 50 mV
External resistors connected to the reference and sense
pins can only increase the gain If ultra-low output imped-
ance is not critical the technique in Figure 5 can be used to
trim the gain to nominal value Alternatively the V_OS adjust-
ment terminals on the 16-pin package may be used to trim
the gain (Figure 10b )
TL H 5609–12
R1 and R2 should be as low as possible to avoid errors due to 50 kX
input impedance of reference and sense pins Total resistance
(R2a2R1) should be above 4 kX however to prevent excessive load
on the LM363 output The exact formula for calculating gain (G) is
 J ^{2R1 R1}
GeG_O
1a a
R2 50k
G_Oepreset gain
The last term may be ignored in applications where gain accuracy is not
critical The table below gives suggested values for R1 and R2 along
with the calculated error due to ‘‘closest value’’ standard 1% resistors
Total gain error tolerance includes contributions from LM363 G_O error
and resistor tolerance (g1%) and works out to approximately 2 5% in
every case
Pinout shown is for 16-pin package This same technique can also be
used with 8-pin versions
Gain Increase
R1
R2
Error (typ)
15
1 21k
5k
a0 6%
2
1 21k
2 49k
b0 2%
25
2k
2 74k
0
3
2k
2 05k
b0 3%
4
1 78k
1 21k
b0 6%
5
2k
1k
a0 8%
6
2 49k
1k
a0 5%
7
2 94k
1k
b0 9%
8
3 48k
1k
a0 4%
9
3 92k
1k
b0 9%
10
4 42k
1k
b0 7%
FIGURE 4 Increasing Gain
Pinout shown is for 8-pin versions
This same technique can also be used
with 16-pin version
TL H 5609 – 13
FIGURE 5 Adjusting Gain Alternate Technique
11