DS90CR481 Datasheet, PDF (11/21 Pages) National Semiconductor (TI) – 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

AC Timing Diagrams (Continued)
C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
Tppos — Transmitter output pulse position (min and max)
RSKM ≥ Cable Skew (type, length) + LVDS Source Clock Jitter (cycle to cycle) + ISI (Inter-symbol interference)
j Cable Skew — typically 10 ps–40 ps per foot, media dependent
j Cycle-to-cycle LVDS Output jitter (TJCC) is less than 100 ps (worse case estimate).
j ISI is dependent on interconnect length; may be zero
See Applications Information section for more details.
FIGURE 13. Receiver Skew Margin (RSKM) for Chipset without DESKEW
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C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
RSKMD ≥ TPPOSvariance (d) + TJCC (output jitter)(f) + ISI (m)
j d= Tppos — Transmitter output pulse position (min and max)
j f= Cycle-to-cycle LVDS Output jitter (TJCC) is less than 100 ps (worse case estimate)
j m= extra margin - assigned to ISI in long cable applications
See Applications Informations section for more details.
FIGURE 14. Receiver Skew Margin (RSKMD) for Chipset with DESKEW
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