DS90C124 Datasheet, PDF (11/17 Pages) National Semiconductor (TI) – 5-35MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

AC Timing Diagrams and Test Circuits (Continued)
FIGURE 13. Deserializer PLL Lock Times and RPWDNB TRI-STATE Delay
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FIGURE 14. Transmitter Output Eye Opening
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FIGURE 15. Receiver Input Tolerance (RxIN_TOL) and Sampling Window
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