SM9503A Datasheet, PDF (8/9 Pages) Nippon Precision Circuits Inc – Radio Controlled Clock Receiver IC

SM9503A
Decoder Circuit
The detector output and peak/bottom hold mid-level potential reference are used to decode the time code sig-
nal, which is output on pin OUT. The output is active-LOW, so that the output is LOW when the input ampli-
tude is HIGH.
VDD potential
Rectifier
LPF
LPF waveform
VDD potential
VDD potential
Peak/
Bottom
Hold
Bottom hold
Mid-level potential
Peak hold
Decoder
VSS potential
OUT output
Standby Function
When PON is open (or HIGH), the device is in standby mode and the current consumption is reduced. Receiver
operation starts when PON goes LOW.
PON
Open (or HIGH)
LOW
Mode
Standby
Operating
OUT
HIGH
Time code
NIPPON PRECISION CIRCUITS INC.—8