SM9503A Datasheet, PDF (7/9 Pages) Nippon Precision Circuits Inc – Radio Controlled Clock Receiver IC

SM9503A
FUNCTIONAL DESCRIPTION
AGC Amplifier and Gain Hold Function
The input voltage from the antenna is amplified by the AGC amplifier. The gain can be monitored by the volt-
age on pin CP, and can be changed by varying the CP voltage. An external capacitor Cp can be connected to CP
to stabilize the voltage, but the gain tracking time is dependent on the capacitance. When HLDN is open (or
HIGH), the gain automatically adjusts to follow the post-amplifier detector signal. When HLDN is LOW, the
immediately preceding gain is held for an interval determined by the Cp capacitance.
Crystal Filter Circuit
External crystals are used as filters. The center frequency and bandwidth of the filters is determined by the
crystal characteristics. If the center frequency is lower than the target frequency, it is necessary to add C_L
capacitor for the adjustment frequency. If Q of the crystal filter is higher and the output delay is larger, it is nec-
essary to add R_L to adjust it. Adding a compensation capacitor C_C, it is possible to select built-in or external,
cancels the high-frequency components pass through the crystal parallel capacitance. Compensation capacitors
are built in, and wiring them inside makes possible to select versions of the required capacitances from 0.5pF
to 2.0pF.
µ
AGC Amp
CC
Post Amp
AGC Amp
CC
Post Amp
XO1 XO2
XI
CC
CL RL
The case of using the external compensation
capacitor
XO1
XO2
XI
CL RL
The case of using built-in compensation capacitor
Detector Circuit
The amplified signal is full-wave rectified and passed through a lowpass filter detector. The detector output is
input to peak hold (pin CP) and bottom hold (pin CB) circuits to form the decoder reference potentials and
peak hold potential for AGC control.
VDD potential
Amplifier
VDD potential
Rectifier
LPF
VDD potential
Peak/
Bottom
Hold
Bottom hold
Peak hold
NIPPON PRECISION CIRCUITS INC.—7