SM9503A Datasheet, PDF (3/9 Pages) Nippon Precision Circuits Inc – Radio Controlled Clock Receiver IC

BLOCK DIAGRAM
SM9503A
PON
OUT
VSS HLDN CP CB
LF
VDD
VDDA
Bias
Decoder
Peak/Bottom
Hold Det.
LPF
AGC Control
IN1
AGC Amp
IN2
CC
Post Amp
Rectifier
VSSA
XO1 XO2
XI
PIN DESCRIPTION
Pad
number
Pin number
Name
I/O ¹
A/D²
1
7
XI
I
A
2
8
LF
O
A
3
9
CB
O
A
4
10
CP
O
A
5
11
HLDN
Ipu
D
6
12
VSS
−
A
7
13
OUT
O
D
8
14
PON
Ipu
D
9
15
VDD
−
A
10
−
VDDA
−
A
11
16
IN2
I
A
12
1
NC
×
×
13
2
IN1
I
A
14
3
NC
×
×
15
4
VSSA
−
A
16
5
XO1
O
A
17
6
XO2
O
A
1. I: input, O: output, Ipu: input with pull-up resistor, –: supply pin
2. A: analog signal, D: digital signal
Description
Crystal filter input connection
Rectifier LPF capacitor connection
Bottom-hold detector capacitor connection
Peak-hold detector capacitor connection
AGC gain hold control (active LOW)
(−) Negative supply input (substrate potential)
Time code output (active LOW)
Standby-mode control input (active LOW)
(+) Positive supply input
(+) Positive supply input (AGC amplifier)
Antenna input 2
No connection (must be open)
Antenna input 1
No connection (must be open)
(−) Negative supply input (AGC amplifier)
Crystal filter output 1
Crystal filter output 2
NIPPON PRECISION CIRCUITS INC.—3