SM5837AF_06 Datasheet, PDF (8/10 Pages) Nippon Precision Circuits Inc – Variable-length 1H Delay Line LSI

SM5837AF
Serial Input Set Method (PARA, SDI, SICK, LEN)
When PARA goes LOW, 3-input serial data set method is used to set the delay length. Inputs DL3 to DL10 are
ignored. SDI, SICK and LEN function as the serial data input, serial data shift clock and latch clock enable,
respectively.
The serial input data format, shown in figure XREF, comprises 11-bit serial data (S0 to S10) input on SDI in
sync with SICK. The data on SDI is clocked into the serial-to-parallel converter shift register on the rising edge
of SICK, and 11-bit parallel data is then latched into the delay length set register on the rising edge of LEN.
The delay length (L_H) is determined by the input data S0 to S10 (just as for parallel input data DL0 to DL10) as
shown in equation 2. See also table 1.
Note that SICK and CLK can be asynchronous.
10
L_H = 31 + _Σ {Sk × 2^k}
(2)
k=0
SDI
S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
SICK
LEN
Dotted lines indicate possible SICK and LEN states.
Figure 1. Serial input data format
Delay Clock Input (CLK)
All 1H delay registers operate in sync with the delay clock CLK. The maximum clock frequency is 40MHz.
Input Data (DI0 to DI11)
DI0 to DI11 are the 12-bit data inputs.
Output Data (DO0 to DO11, OE)
DO0 to DO11 are the 12-bit data outputs. They are tristate outputs, with the output state selected by OE. When
OE is HIGH, the outputs are enabled. When OE is LOW, the outputs are disabled (high-impedance state).
Reset (RSTN)
At power-ON, the internal timing generator circuits must be initialized by a LOW-level input on RSTN. After
RSTN goes HIGH, the set delay length becomes active.
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