SM5837AF_06 Datasheet, PDF (2/10 Pages) Nippon Precision Circuits Inc – Variable-length 1H Delay Line LSI

BLOCK DIAGRAM
SM5837AF
12
DI0 - 11
CLK
RSTN
PARA
SDI
SICK
LEN
Variable-length
12
12-bit
1H Delay
Delay Length Control
11
Parallel/Serial Select
11
SIPO
11
DL0 - 10
12
DO0 - 11
OE
VDD
VSS2
VSS1
PIN DESCRIPTION
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Name
DL0/SDI
DL1/SICK
DL2/LEN
DL3
DL4
VSS1
DL5
DL6
DL7
DL8
DL9
DL10
DO0
DO1
DO2
DO3
VSS2
DO4
DO5
DO6
DO7
I/O ¹
Function
Ip Delay length set parallel data bit DL0 (LSB) when PARA is HIGH, and SDI serial data input when PARA is LOW.
Ip Delay length set parallel data bit DL1 (bit 1) when PARA is HIGH, and SICK shift clock when PARA is LOW.
Ip Delay length set parallel data bit DL2 (bit 2) when PARA is HIGH, and LEN latch clock when PARA is LOW.
Ip Delay length set data bit 3
Ip Delay length set data bit 4
– Ground (0V) pin 1
Ip Delay length set data bit 5
Ip Delay length set data bit 6
Ip Delay length set data bit 7
Ip Delay length set data bit 8
Ip Delay length set data bit 9
Ip Delay length set data bit 10
O Signal output data bit 0
O Signal output data bit 1
O Signal output data bit 2
O Signal output data bit 3
– Ground (0V) pin 2
O Signal output data bit 4
O Signal output data bit 5
O Signal output data bit 6
O Signal output data bit 7
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