SM5165AV Datasheet, PDF (8/10 Pages) Nippon Precision Circuits Inc – PLL Synthesizer IC

SM5165AV
Operating principles
When the PLL is operating with a phase error within
fixed tolerance, an internal WINDOWN signal is
generated. This signal is in sync with the N counter
output signal (FV) and is 62 cycles of the FIN input
period in length centered about the falling edge of
FV.
If the phase detector error correction signal occurs
before the WINDOWN LOW-level pulse, the HIGH-
level output from DB continues. However, if the
error correction signal occurs wholly within the
WINDOWN LOW-level pulsewidth, DB goes high
impedance and the boost-up circuit operation stops.
The above description applies when the error correc-
tion signal is revising up. When the error correction
signal is revising down, DB goes LOW.
Standby Mode
The SM5165AV enters standby mode when OPR
goes LOW. In this mode, the following pin states and
functions occur.
Function
Outputs DO and
DB
Phase detector
Input FIN
Input XIN
N counter
R counter
Latch data
State
Floating (high impedance)
Reset
Feedback resistor is cutoff (internal HIGH level)
Feedback resistor is cutoff (internal HIGH level)
Reset
Reset
Stored
Note that even in standby mode, some current flows
into VDD1 (FIN and XIN prescaler current). It is
recommended that VDD1 be grounded in standby
mode to reduce current consumption if necessary.
Note also that the above pin states and functions are
only valid if V_DD2 and V_DD3 are maintained within
normal operating conditions. If V_DD2 and/or V_DD3
are not within normal operating conditions, the latch data is not retained.
Phase Comparator Timing Diagram
FR
FV
DO
LD
FV and FR are the internal comparator frequency divider output signal and reference frequency divider output signal, respectively.
Passive Low-pass Filter
R1
DO
VCO
R2
C
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