SM5165AV Datasheet, PDF (7/10 Pages) Nippon Precision Circuits Inc – PLL Synthesizer IC

SM5165AV
Reference counter frequency divider setting
MSB
LSB
DATA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
No meaning
Test bits
2 ¹⁰ 2 ⁹ 2 ⁸ 2 ⁷ 2 ⁶ 2 ⁵ 2 ⁴ 2 ³ 2 ² 2 ¹ 2 ⁰ No
Reference counter
meaning
(11-bit : 5 to 8191)
Latch select bit. Set "0"
Bits 1 to 7 and bits 21 and 22 have no meaning. These bits should be set to 0.
Bits 8 and 9 are used for testing at the manufacturers and should be set to 1 and 0, respectively, for normal
operation.
Input data example
If the VCO output is (f_VCO) trebled, the crystal oscillator frequency is 12.8 MHz and the channel bandwidth
(f_CH: comparator frequency (f_R) × 3) is 25 kHz, then the reference frequency divider ratio R is given by:
NR
=
X-----t--a---l
f_CH
=
-f--X_R----t-_×-a---l-3-
=
0---.--01---22---5.--8--⁄^---3-
=
1536
=
8 × 192
Therefore, the reference counter count is 192 (00011000000)₂.
MSB
LSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Input
2 ¹⁰ 2 ⁹ 2 ⁸ 2 ⁷ 2 ⁶ 2 ⁵ 2 ⁴ 2 ³ 2 ² 2 ¹ 2 ⁰
Data ^{0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0}
No meaning
No
Reference counter
meaning
Test bits
(11-bit : 5 to 8191)
Latch select bit. Set "0"
Boost-up Signal
When the PLL starts up with some phase tolerance, a
level signal is output on pin DB. When the PLL
phase error comes within the tolerance before in
lock, output DB goes high impedance.
When the PLL starts up, the signal on DB charges
the low-pass filter capacitor in anticipation of high-
speed locking. After the boost-up signal is output and
the PLL phase error comes within tolerance, the
boost-up circuit stops and operation continues when
the 3 supplies (V_DD1, V_DD2) are applied and OPR
goes HIGH once only. After the boost-up circuit
stops, new data is written and the boost-up signal is
not output even if the VCO is not in lock.
FR
FV
Phase detector
error correction signal
WINDOWN
DB
(High impedance)
∗∗
∗^{( : 32fFIN )}
(HIGH level output)
∗∗
(High impedance)
NIPPON PRECISION CIRCUITS—7