SM5165AV Datasheet, PDF (6/10 Pages) Nippon Precision Circuits Inc – PLL Synthesizer IC

SM5165AV
Latch select
The last (23rd) data bit determines the shift register data latch.
Bit 23
0
1
Latch
Reference frequency counter divider ratio data latch
select
Swallow counter and main counter frequency divider
ratio and DO output latch select
Swallow counter, main counter frequency divider data and DO output
MSB
LSB
DATA ^{1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23}
2 ¹² 2 ¹¹ 2 ¹⁰ 2 ⁹ 2 ⁸ 2 ⁷ 2 ⁶ 2 ⁵ 2 ⁴ 2 ³ 2 ² 2 ¹ 2 ⁰ 2 ⁴ 2 ³ 2 ² 2 ¹ 2 ⁰ No
Main counter
Swallow counter ^meaning
(13-bit : 32 to 8191)
(5-bit : 0 to 31)
Latch select bit. Setting "1"
DO output select bits
Bits 19 and 20 have no meaning. These bits should be set to 0.
Bits 20 and 21 control the state of the DO output pin.
Bit 21
0
1
0
1
Bit 22
0
0
1
1
DO output
High impedance
Normal operation
The DO output polarity can be set by master-slice for either a passive or active filter.
Input data example
If the VCO output is (f_VCO) trebled, the output frequency (f_LO) is 251.3 MHz, and the channel bandwidth (f_CH:
comparator frequency (f_R) × 3) is 25 kHz, then the comparator frequency divider ratio N is given by:
N
=
-f--^L----^O--
f_CH
=
f---_{V--f--RC----O-×-----}×_3----3--
=
20---5.--0-1--2-.--35----⁄⁄_---33-
=
10052
=
32 × 314 + 4
Therefore, the swallow counter count is 4 (00100)₂ and the main counter count is 314 (0000100111010)₂.
MSB
LSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Input ^{2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 4 2 3 2 2 2 1 2 0}
Data ^{0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 1 0 0 0 0 1 1 1}
Main counter
No
Swallow counter _meaning
(13-bit : 32 to 8191)
(5-bit : 0 to 31)
Latch select bit. Setting "1"
DO output select bits
NIPPON PRECISION CIRCUITS—6