SM9501B Datasheet, PDF (7/8 Pages) Nippon Precision Circuits Inc – Radio Controlled Clock Receiver IC

Crystal Filter Circuit
SM9501B
XO
Cx40
Cx60
Rx40
Rx60
XI
40kHz
60kHz
External crystals are used as filters. Multiple frequencies (40kHz and 60kHz) are supported by connecting
crystals in parallel. The center frequency and bandwidth of the filters is determined by the crystal characteris-
tics. If the center frequency is lower than the target frequency, C×40 and C×60 can be added to change the res-
onant frequency. And R×40 and R×60 can be added to adjust the filter Q factor. Internally, pin XO is linked to
pin XI by a phase-inverted signal passed through a capacitor, which cancels the high-frequency components
that pass through the crystal parallel capacitances.
Detector Circuit
The amplified signal is full-wave rectified and passed through a lowpass filter detector. The detector output is
input to peak hold (pin CP) and bottom hold (pin CB) circuits to form the decoder reference potentials and
peak hold potential for AGC control.
Amplifier
VSS potential
Rectifier
LPF
VSS potential
Peak/
Bottom
Hold
VSS potential
Peak hold
Bottom hold
Decoder Circuit
The detector output and peak/bottom hold mid-level potential reference are used to decode the time code sig-
nal, which is output on pin OUT. The output is active-LOW, so that the output is LOW when the input ampli-
tude is HIGH.
Rectifier
LPF
LPF waveform
VDD potential
VSS potential
Decoder
OUT output
Peak/
Bottom
Hold
VSS potential
Peak hold
Mid-level potential
Bottom hold
VSS potential
Standby Function
When PON is open (or HIGH), the device is in standby mode and the current consumption is reduced. Receiver
operation starts when PON goes LOW.
PON
Open (or HIGH)
LOW
Mode
Standby
Operating
OUT
HIGH
Time code
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