SM9501B Datasheet, PDF (6/8 Pages) Nippon Precision Circuits Inc – Radio Controlled Clock Receiver IC

SM9501B
FUNCTIONAL DESCRIPTION
Antenna Input and Tuning Capacitor Switching Function
FCN
C1 C2 _IN1
IN3
L1
IN2
AGC
There are three antenna inputs: IN1, IN2, and IN3. When FCN is open (or HIGH), the internal analog switch is
OFF and IN1–IN2 are the antenna inputs (60kHz mode). When FCN is LOW, the analog switch is ON, con-
necting IN3 and IN2. C2 is then connected in parallel to C1 in the tuning circuit, reducing the resonant fre-
quency (40kHz mode).
FCN
Open or HIGH
LOW
Analog switch
OFF
ON
Antenna input
Between IN1 and IN2
Between IN1 and IN2, IN3
Tuning capacitor
C1
C1 + C2 parallel
Receiver frequency
60kHz
40kHz
FCN should be left open if not using the tuning capacitor switching function, and IN2 should be connected to
IN3 externally.
AGC Amplifier and Gain Hold Function
The input voltage from the antenna is amplified by the AGC amplifier. The gain can be monitored by the volt-
age on pin CP, and can be changed by varying the CP voltage. An external capacitor Cp can be connected to CP
to stabilize the voltage, but the gain tracking time is dependent on the capacitance. When HLDN is open (or
HIGH), the gain automatically adjusts to follow the post-amplifier detector signal. When HLDN is LOW, the
immediately preceding gain is held for an interval determined by the Cp capacitance.
HLDN
Open or HIGH
LOW
Gain tracking
Auto tracking
Gain held fixed
HLDN
AGC Amp
Peak Hold Detector
Bottom Hold Detector
CP
CB
Cb Cp
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