SM9501B Datasheet, PDF (2/8 Pages) Nippon Precision Circuits Inc – Radio Controlled Clock Receiver IC

BLOCK DIAGRAM
SM9501B
VDD
VDDA
IN1
PON
Bias
OUT
VSS HLDN CP CB
Decoder
AGC Control
Peak/Bottom
Hold Det.
AGC Amp
Post Amp
IN3
IN2
FCN
XO VSSA XI
Rectifier
LPF
LF
PIN DESCRIPTION
Number
Name
I/O ¹
A/D²
Description
1
VDDA
−
A
AGC amplifier (+) supply input
2
IN1
I
A
Antenna input 1 (fixed input)
3
IN3
I
A
Antenna input 3 (via analog switch)
4
IN2
I
A
Antenna input 2 (analog switch bypass)
5
FCN
Ipu
D
Analog switch control input (active LOW)
6
XO
O
A
Output for crystal filter
7
VSSA
−
A
AGC amplifier (–) supply input
8
XI
I
A
Input from crystal filter
9
LF
O
A
Rectifier LPF capacitor connection
10
CB
O
A
Bottom hold detector capacitor connection
11
CP
O
A
Peak hold detector capacitor connection
12
HLDN
Ipu
D
AGC gain hold control (active LOW)
13
VSS
−
A
Substrate (–) supply input
14
OUT
O
D
Clock time code output (active LOW)
15
PON
Ipu
D
Standby state control input (active LOW)
16
VDD
−
A
(+) supply input
−
TN
Ipu
D
AGC amplifier gain control switch (active LOW, for test mode)
1. I: input, O: output, Ipu: input with pull-up resistor, –: supply pin
2. A: analog signal, D: digital signal
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