SM5842AP Datasheet, PDF (3/23 Pages) Nippon Precision Circuits Inc – High-Class Audio Multi-function Digital Filter

SM5842AP/APT
PIN DESCRIPTION
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Name
DI/INF2N
BCKI
CKSLN
INF1N
IW1N/DIL
XTI
XTO
VSS
CKO
IW2N/DIR
OW1N
OW2N
SYNCN
RSTN
DEMPR
DEMPR
FSEL1
FSEL2
I/O ¹
Description
Ip
Data input when INF1N is LOW, and input format select pin 2 when INF1N is HIGH.
Ip
Input bit clock
Ip
Oscillator and system clock select input. 384fs when HIGH, and 256fs when LOW.
Input format select pin 1. INF1N and INF2N select the pin functions below.
INF1N DI/INF2N
Input format
Pin function selection
DI/INF2N IW1N/DIL IW2N/DIR
Ip
LOW
LOW
LR alternating, trailing data
DI
IW1N
IW2N
LOW
HIGH
HIGH
LOW LR alternating, leading data
INF2N
DIL
DIR
HIGH
HIGH LR simultaneous, leading data
Input bit length select pin 1 when INF1N is LOW, and left-channel data input when INF1N is HIGH.
IW1N and IW2N select the input data length.
INF1N
IW2N/DIL
IW1N/DIR
Input bit length
LOW
LOW
24 bits
Ip
LOW
LOW
HIGH
HIGH
LOW
20 bits
18 bits
HIGH
HIGH
16 bits
HIGH
×
×
24 bits
I
Oscillator input connection
O
Oscillator output connection
–
Ground
O
Oscillator output clock. Same frequency as XTI.
Ip
Input bit length select pin 2 when INF2N is LOW, and right-channel data input when INF2N is HIGH.
IW1N and IW2N select the input data length as shown in the table for pin 5.
Output length select bits.
Ip
OW2N
LOW
OW1N
LOW
Output bit length
24 bits
LOW
HIGH
22 bits
Ip
HIGH
HIGH
LOW
HIGH
20 bits
18 bits
Ip
Sync mode select pin. Normal sync mode when LOW, and jitter-free mode when HIGH.
Ip
System reset. Reset operation when LOW, and normal operation when HIGH.
Ip
Right-channel deemphasis control signal. OFF when LOW, and ON when HIGH.
Ip
Left-channel deemphasis control signal. OFF when LOW, and ON when HIGH.
Deemphasis filter select inputs
Ip
FSEL1
LOW
FSEL2
LOW
Sampling frequency (fs)
44.1 kHz
LOW
HIGH
48 kHz
Ip
HIGH
HIGH
LOW
HIGH
Invalid setting
32 kHz
NIPPON PRECISION CIRCUITS—3