SM5842AP Datasheet, PDF (14/23 Pages) Nippon Precision Circuits Inc – High-Class Audio Multi-function Digital Filter

SM5842AP/APT
Audio Data Input (INF1N, INF2N, IW1N, IW2N, DI, DIL, DIR, BCKI, LRCI)
The input data format and several input pin functions
are selected by the state of INF1N and INF2N as
shown in table 3.
Table 3. Pin function select
INF1N
DI/INF2N
Input format
Pin function selection
DI/INF2N
IW1N/DIL
IW2N/DIR
LOW
LOW
LOW
HIGH
LR alternating¹, trailing data
DI
IW1N
IW2N
HIGH
HIGH
LOW
HIGH
LR alternating, leading data
LR simultaneous², leading data
INF2N
DIL
DIR
1. Alternating left-channel and right-channel data input on a single input DI.
2. Simultaneous left-channel and right-channel data input on two inputs, DIL and DIR, respectively.
The input data word length is selected by the state of
IW1N and IW2N when INF1N is LOW. 24-bit is
selected when INF1N is HIGH.
Table 4. Input word length
INF1N
LOW
HIGH
IW2N/DIL
LOW
LOW
HIGH
HIGH
×
IW1N/DIR
LOW
HIGH
LOW
HIGH
×
Input word length
24 bits
22 bits
18 bits
16 bits
24 bits
Jitter-free Function (SYNCN)
The arithmetic circuit and output control timing is
derived from the system clock, and is therefore inde-
pendent of the input LRCI and BCKI clocks.
Accordingly, any jitter in the data input clock (LRCI
and BCKI) does not cause jitter in the output.
Generally, the internal timing is synchronized to the
LRCI input timing after a system reset release, when
RSTN goes from LOW to HIGH, on the first LRCI
clock start edge. If the input timing and LRCI start
edge timing subsequently drift, the input timing is
automatically resynchronized when the timing error
exceeds a certain value. There are 2 timing error val-
ues at which resynchronization occurs, selected by
the state of SYNCN.
Jitter-free mode (SYNCN = HIGH)
When SYNCN is HIGH, the timing error value is
±3/8 × (LRCI clock period). When the difference
between the input timing and LRCI start edge posi-
tion do not exceed this value, internal timing is not
resynchronized and all functions continue to operate
normally.
Sync mode (SYNCN = LOW)
When SYNCN is LOW, the timing error value is ±1
× (system clock period), which is a much smaller
timing error tolerance than in jitter-free mode. In this
mode, the internal timing is guaranteed to follow the
LRCI clock timing within this tolerance, making this
mode useful for systems constructed from a multiple
number of SM5842AP/APT devices.
Note that resynchronization affects the internal oper-
ation and can generate a momentary click noise out-
put.
NIPPON PRECISION CIRCUITS—14