SM8707 Datasheet, PDF (18/20 Pages) Nippon Precision Circuits Inc – Clock Generator with Dual PLLs

SM8707 series
Spike Noise Prevention Function
All device versions, excluding the SM8707G which has no FSEL input, have a spike noise prevention circuit
that prevents any spike noise generation in the audio output clocks when the sampling frequency is switched
using FSEL.
The state of the AO× output before and after FSEL is switched is shown in Figure 7.
When FSEL is switched, either from LOW to HIGH or HIGH to LOW, the spike noise prevention circuit stops
the AO× clock output by a maximum of 1µs, and then the output clock changes to reflect the current FSEL set-
ting.
fs = 44.1kHz
(SM8707E: fs = 48kHz)
FSEL
fs = 48kHz
(SM8707E: fs = 44.1kHz)
AO
1µs (max)
Figure 7. Spike noise prevention circuit timing at sampling frequency switching
Sampling Frequency Switching Settling Time
The clock output response when the sampling frequency is switched using FSEL is shown in Figure 8. Note
that all device versions, excluding the SM8707G which has no FSEL input, have a spike noise prevention cir-
cuit which stops the output AO× clocks for a fixed interval, which means the settling time is a maximum 1µs
when the sampling frequency is switched.
FSEL
0.8VDD
tS
AO
fs = 48kHz
(SM8707E: fs = 44.1kHz)
0.2VDD
tS
fs = 44.1kHz
(SM8707E: fs = 48kHz)
fs = 48kHz
(SM8707E: fs = 44.1kHz)
MO
27.0000MHz
SO
16.9344/33.8688MHz (SM8707D/F)
33.8688MHz (SM8707E)
16.9344/33.8688/36.8640MHz (SM8707H)
18.4320/24.5760/33.8688/36.8640MHz (SM8707K)
24.5760/33.8688MHz (SM8707L)
Figure 8. Output signal switching timing
NIPPON PRECISION CIRCUITS INC.—18