SM5819HQF Datasheet, PDF (15/18 Pages) Nippon Precision Circuits Inc – 6-channel DSD-PCM Converter

SM5819HQF
DSD Gain Switching
The PCM output can be adjusted such that 0dB corresponds to 50% modulation level DSD input signal using
DSGAIN, as given below.
DSGAIN = “L” : 100% modulation = 0dB (PCM)
DSGAIN = “H” : 50% modulation = 0dB (PCM) * with +6dB internal amplification
+1.0
+0.5
0dB when
DSGAIN="H"
[7FFFFFFFh]
0dB when
DSGAIN="L"
[7FFFFFFFh]
0
[00000000h]
[00000000h]
-0.5
[80000000h]
-1.0
[80000000h]
Figure 4. DSD modulation level
Note. When DSGAIN = “H”, note that any input DSD signal with modulation of 50% level or higher will be amplitude limited, resulting in output signal clip-
ping.
Note. In the case of 4fs mode, the PCM data is a setting which passes through passband. When the DSGAIN is set to HIGH, it may clip depending on sig-
nal. Therefore, please use at DSGAIN = LOW.
Mute Function
The PCM outputs can be muted using XMTPCM, as given below. Muting is applied immediately before output.
When PCM muting is set ON, the PCM outputs are directly set to value “0”.
XMTPCM = “L” : all PCM outputs muting ON
XMTPCM = “H” : all PCM outputs muting OFF
The mute function is only active for internal computation of fs/2fs/4fs output. It is inactive for external input to
output connection in through mode.
Initialization Operation
The power must be applied in order of VDDL and VDDH. Please avoid the continuous power supply injection
of only VDDH. (less than 1 second)
After power is applied, INIT must be held LOW for the rated interval to initialize the device. During initializa-
tion, the outputs have the following states.
Pin
PCM data outputs
DSBCK
PBCK
PLRCK
MCKOUT
state
LOW in internal data output mode
External input to output connection in through mode
HIGH in output (master) mode
HIGH in internal data output mode
External bit clock input to output connection in through mode
LOW in 32-bit left-justified output mode
HIGH in IIS output mode
External word clock input to output connection in through mode
MCK or EXIMCK, whichever is currently selected.
When INIT goes HIGH, synchronization operation begins as described in the section “Input clock sync opera-
tion and resynchronization”.
Note that if the PCM signal muting is ON during initialization, muting operation continues until it is released.
The system clock input on MCK must be applied during initialization.
NIPPON PRECISION CIRCUITS INC.—15