SM5819HQF Datasheet, PDF (12/18 Pages) Nippon Precision Circuits Inc – 6-channel DSD-PCM Converter

SM5819HQF
Data Output Selection
PCM output selection
The PCM output and decimation filter processing is set by SEL4FS, SEL1FS and SELEXT, as shown in the
following table.
Setting
SEL1FS SEL4FS SELEXT
L
H
L
L
L
L
H
L or H
L
L or H
L or H
H
POFLR
DSIFL
DSIFR
DSIFL
DSIFR
DSIFL
DSIFR
EXIFLR
PCM output system
POSLR
DSISL
DSISR
DSISL
DSISR
DSISL
DSISR
EXISLR
POCSW
DSICT
DSISW
DSICT
DSISW
DSICT
DSISW
EXICSW
PLRCK
PBCK
4fs
2fs
fs
EXILRCK
EXIBCK
Clock
output
MCKOUT
Filter
processing
MCK
4fs
960th-order
MCK
2fs
960th-order
MCK
fs
960th-order
EXIMCK
Invalid
I The external data setting (SELEXT) has priority over the 4fs/2fs/fs selection setting (SEL1FS, SEL4FS).
I Also, the fs setting (SEL1FS) has priority over the 4fs/2fs setting (SEL4FS).
I In the case of 4fs mode, the PCM data is a setting which passes through passband. When the DSGAIN is set
to HIGH, it may clip depending on signal. Therefore, please use at DSGAIN = LOW.
Clock Input/Output Selection and Resynchronization Operation
DSD clock input/output switching
The DSD input bit clock (DSBCK) can be switched between input and output by DIRDSCK.
Setting
DIRDSCK
L
H
I/O state
DSBCK
Input (Slave)
Output (Master)
PCM clock input/output switching
The PCM output word clock (PLRCK) and bit clock (PBCK) can be switched between input and output by
DIRPCK.
Setting
DIRPCK
L
H
I/O state
PLRCK
PBCK
Output (Master)
Input (Slave)
However, when external data is selected using SELEXT, the clocks PLRCK and PBCK are switched to outputs,
regardless of the DIRPCK setting, thus care must be exercised with external connections.
NIPPON PRECISION CIRCUITS INC.—12