SM5819HQF Datasheet, PDF (13/18 Pages) Nippon Precision Circuits Inc – 6-channel DSD-PCM Converter

SM5819HQF
Input clock sync operation and resynchronization
The internal computation and interface processing for data output is event driven, with the word boundary edge
of the word clock as the trigger. This ensures the output signals are synchronized, regardless of the word clock
and bit clock input/output settings.
The DSD input comprises data read into a buffer on the rising edge of the DSBCK bit clock (BUF_A) and data
in another buffer internally delayed by half a bit clock cycle (BUF_B), and then a buffer is selected when the
PCM output event occurs in order to avoid DSD input signal transitions.
Synchronization of whichever data buffer is selected occurs when the word boundary edge of the word clock is
detected after the first DSBCK falling edge following a rising edge on INIT or SYNC.
SNYC/INIT
DSI**
;;;;;;;;;;;;;;;;;;;;;;;;;;;;
D (n)
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;^{D (n+1)};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ^{D (n+2)} ;;;;;;;;;;;;;;;;;;;;;;;;;;;; ^{D (n+3)} ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ^{D (n+3)} ;;;;;;;;;;;;
DSBCK
(BUF_A)
(BUF_B)
(IN_PHASE)
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;^D;;;;;;;;;;;^{B;;;;;;;;;;;(;;;;;;;;;;;n-;;;;;;;;;;;1;;;;;;;;;;;) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;D;;;;;;;;;;;A;;;;;;;;(;;;;n;;;;) ;;;;;;;;D;;;;B;;;;(n)}
DA (n+1)
DA (n+2)
DA (n+3)
DB (n+1)
DB (n+2)
DB (n+2)
(PCM_SEL) _{;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;}(_;;;;S_;;;;e_;;;;le_;;;;ct_;;;;"_;;;;B_;;;;U_;;;;F_;;;;_A_;;;;"_;;;;)_{;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;}
PLRCK
(Filter Input) _{;;;;;;;;;;;;;;;;;;;;}D_;;;;A_;;;;(_;;;;n-_;;;;1_;;;;) _{;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;}D_;;;;A_;;;;(_;;;;n)_{;;;;;;;;;;;;;;;;;;;;;;;;;;;;}D_;;;;A_;;;;;;;;(n_;;;;+_;;;;1_;;;;) _;;;;;;;;
(Word boundary edge)
DB (n+1)
DB (n+2)
DSI**: DSIFL, DSIFR, DSISL, DSISR, DSICT, DSISW pins
Figure 1. Input timing synchronization operation using INIT and SYNC
1) On the first DSBCK falling edge after a rising edge of SYNC or INIT, (IN_PHASE) is a phase reference sig-
nal for input data buffer selection.
2) Then, the input data buffer selected is determined by the logic level of IN_PHASE when the first PLRCK
word boundary edge is detected.
When synchronization is adjusted using INIT or SYNC (resynchronization), 1 DSD data unit may be lost or
repeated depending on the phase difference between input/output clocks.
The individual outputs should be muted by a minimum interval, given below, to avoid these data glitches.
[4fs PCM output] 36 clock cycles in PLRCK (4fs) mode
[2fs PCM output] 18 clock cycles in PLRCK (2fs) mode
[fs PCM output] 10 clock cycles in PLRCK (fs) mode
NIPPON PRECISION CIRCUITS INC.—13