SM8703CV Datasheet, PDF (11/12 Pages) Nippon Precision Circuits Inc – Clock Generator for DVD Players

TYPICAL APPLICATION
SM8703CV
+3.3V
CPU
+3.3V
VDD
MO2
C3
VSS
FSEL/MDT
MO1
SO5
MCK
RSV
MLEN
SO2
VDDA
VDD1
C4
C5
VSSA
VSS1
XTI
C1 _X'tal
XTO
C2
RSV
RSV
SO3
SO4
RSV
VDD2
C6
SO1
VSS2
SM8703CV
27MHz
27MHz
768fs
384fs
512fs
512fs
33.8688MHz
I Connect the decoupling capacitors (approximately
0.1µF and 1000pF) in parallel, as close to the
power supply pins as possible.
I A solid VSS pattern beneath the IC should be used
to minimize noise.
I Master clock stability affects the stability of the
other outputs. If a crystal oscillator is used, the
oscillator element and load capacitors should be
placed as close to the SM8703CV as possible, and
connected with wires as short as possible. The
crystal oscillator element and load capacitor com-
bination has an effect on frequency accuracy, and
the load capacitors (C1, C2) should be selected to
match the required application.
I The SM8703CV outputs several high-frequency
clocks, so the supply wiring pattern (including
decoupling capacitors) should be considered care-
fully. In particular, the output supply wiring and
PLL supply wiring should separated to prevent
noise insertion. The output wiring capacitance
should be minimized as much as possible to pre-
vent noise. If necessary, the output clocks can be
buffered.
I Power supply and VSS pins.
• VDD : Power supply for digital block
(CPU I/F*, MO1, MO2)
• VSS : VSS for digital block
(CPU I/F*, MO1, MO2)
• VDDA : Power supply for PLL block
(XTI, XTO, PLL/VCO)
• VSSA : VSS for PLL block
(XTI, XTO, PLL/VCO)
• VDD1 : Power supply for output block
(except SO1)
• VSS1 : VSS for output block
(except SO1)
• VDD2 : Power supply for SO1
• VSS2 : VSS for SO1
*: CPU I/F: FSEL/MDT, MLEN, MCK
SEIKO NPC CORPORATION —11