IRF830 Datasheet, PDF (4/7 Pages) NXP Semiconductors – PowerMOS transistor Avalanche energy rated

SEMICONDUCTOR
Fig.5 Typical capacitance vs. Drain-to-Source
voltage
1500
1250
1000
750
VGS = 0V, f =1MHz
Ciss = Cgs +Cgd (Cds = shorted )
Crss = Cgd
Coss = Cds +Cgd
Ciss
500
Coss
Crss
250
0
10⁰
10¹
Drain-to-Source voltage , V_DS (V)
IRF830 Series RRooHHSS
Nell High Power Products
Fig.6 Typical source-drain diode forward
voltage
10¹
150°C
25°C
10⁰
V_GS=0V
0.4
0.6
0.8
1.0
1.2
Source-to-drain voltage, V_SD (V)
Fig.7 Typical gate charge vs. drain-to-source
voltage
20
I_D = 3.1 A
16
VDS = 400V
VDS = 250V
12
VDS = 100V
8
4
For test circuit
See figure 13
0
0
8
16
24
32
40
Total gate charge , Q_G (nC)
Fig.8 Maximum safe operating area
10²
Operation in This Area is Limited by RDS(ON)
10µs
10
100µs
1ms
1
10ms
0.1
10-²
0.1
1
Note:
1. TC = 25°C
2. T_J = 150°C
3. Single Pulse
10
10²
10³
10⁴
Drain-to-Source voltage, V_DS (volts)
Fig.9 Maximum drain current vs.
Case temperature
5
4
3
2
1
0
25
50
75
100
125
150
Case temperature, T_C (°C)
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