TIP41 Datasheet, PDF (3/5 Pages) Mospec Semiconductor – POWER TRANSISTORS(6A,40-100V,65W)

SEMICONDUCTOR
TIP41 (NPN) Series
TIP42 (PNP) Series ^RRooHHSS
Nell High Power Products
T_A T_C
4.0 80
Fig.1 Power Derating
3.0 60
2.0 40
1.0 20
T_C
T_A
00
0 20 40 60 80 100 120 140 160
Temperature, T (°C)
Fig.2 Switching time test circuit
V_CC
+30 V
+11 V
0
-9.0 V
25 µs
t _r , t_{f ≤ 10 ns}
DUTY CYCLE = 1.0%
Rc
SCOPE
R_B
D₁
-4 V
R_B and R _C VARIED TO OBTAIN DESIRED CURRENT LEVELS
D₁ MUST BE FAST RECOVERY TYPE, e.g.:
1N5825 USED ABOVE I_{B ≈} 100 mA
MSD6100 USED BELOW I_{B ≈}100 mA
Fig.3 Active region safe operating area
10
5.0
T_J = 150°C
3.0 _{CURVES APPLY}
1.0ms
2.0 ^{BELLOW RATED V}CEO
Second Breakdown Limited
1.0
Thermal limit @ T_J = 25˚C
(Single pulse)
0.5
Bonding wire limit
0.5ms
5.0ms
0.3
0.2
0.1
5.0
TIP41.TIP42
TIP41A,TIP42A
TIP41B,TIP42B
TIP41C,TIP42C
10 20
40
60 80100
There are two limitations on the power handling ability of a transistor:
average junction temperature and second breakdown. Safe operating
area curves indicate l_C-V_CE limits of the transistor that must be observed
for reliable operation; i.e., the transistor must not be subjected to greater
dissipation than the curve indicate.
The data of fig.3 is based on T_J(pk) = 150°C; T_C is variable depending on
conditions. Second breakdown pulse limits are valid for duty cycles to10%
provided T_J(pk) ≤ 150°C. T_J(pk) may be calulated form the data in Figure 13.
At high case temperatures, thermal limitations will reduce the power that
can be handled to values less than the limitations imposed by second
breakdown.
Collector-emitter voltage , V_CE (V)
Fig.4 Turn-on time
2.0
1.0
0.7
0.5
0.3
0.2
0.1
0.07
0.05
0.03
0.02
0.06 0.1
T_J = 25°C
V_CC = 30V
I_C/I_B = 10
t_r
t_d @ V_BE(off) ≈ 5.0V
0.2 0.4 0.6 1.0 2.0 4.0 6.0
Collector Current, l_C (A)
Fig.5 Turn-off time
5.0
3.0
2.0
1.0
0.7
0.5
0.3
0.2
0.1
0.07
0.05
0.06 0.1
I_B1= I_B2
I_C / I_B = 10
V_CC = 30V
T_J = 25°C
t_S
t_f
0.2 0.4 0.6 1.0 2.0 4.0 6.0
Collector current , I_C (A)
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