UPD75517 Datasheet, PDF (91/180 Pages) NEC – 4 BIT SINGLE-CHIP MICROCOMPUTER

µPD75517(A)
Fig. 4-36 Format of Serial Bus Interface Control Register (SBIC) (2/3)
Bus release trigger bit (W)
RELT Control bit for bus release signal (REL) trigger output.
By setting RELT = 1, the SO0 latch is set to 1. Then the RELT bit is automatically cleared to 0.
Caution Never clear SB0 (or SB1) during serial transfer. Be sure to clear SB0 (or SB1) before or after serial
transfer.
Command trigger bit (W)
CMDT Control bit for command signal (CMD) trigger output.
By setting CMDT = 1, the SO0 latch is cleared to 0. Then the CMDT bit is automatically cleared to 0.
Caution Never clear SB0 (or SB1) during serial transfer. Be sure to clear SB0 (or SB1) before or after serial
transfer.
Bus release detection flag (R)
RELD
Condition for being cleared (RELD = 0)
1 The transfer start instruction is executed.
2 The RESET signal is entered.
3 CSIE0 = 0 (See Fig. 4-35.)
4 SVA does not match SIO0 when an address is
received.
Condition for being set (RELD = 1)
The bus release signal (REL) is detected.
Command detection flag (R)
CMDD
Condition for being cleared (CMDD = 0)
1 The transfer start instruction is executed.
2 The bus release signal (REL) is detected.
3 The RESET signal is entered.
4 CSIE0 = 0 (See Fig. 4-35.)
Condition for being set (CMDD = 1)
The command signal (CMD) is detected.
Acknowledge trigger bit (W)
ACKT When set after transfer, ACK is output in phase with the next SCK0. After ACK signal output, this bit is auto-
matically cleared to 0.
Cautions 1. Never set ACKT before or during serial transfer.
2. ACKT cannot be cleared by software.
3. Before setting ACKT, set ACKE = 0.
Acknowledge enable bit (R/W)
ACKE
0
Disables automatic output of the acknowledge signal (ACK). (Output by ACKT is possible.)
1
When set before transfer
ACK is output in phase with the 9th clock of SCK0.
When set after transfer
ACK is output in phase with SCK0 immediately following set
instruction execution.
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