UPD75517 Datasheet, PDF (167/180 Pages) NEC – 4 BIT SINGLE-CHIP MICROCOMPUTER

µPD75517(A)
(2) Serial transfer
(a) Two-wire and three-wire serial I/O modes (SCK ... Internal clock output):
Parameter
SCK cycle time
SCK high/low level
width
SI setup time
(referred to SCK↑)
SI hold time
(referred to SCK↑)
SCK↓ → SO output
delay time
Symbol Min.
tKCY1
1600
1340
3800
2680
tKL1
tKCY/2 – 50
tKH1
tKCY/2 – 150
tSIK1
150
Typ.
tKSI1
400
tKSO1
Max.
250
1000
Unit
ns
ns
ns
ns
ns
ns
ns
Conditions
VDD = 4.5 to 6.0 V fX = 4.19 MHz
VDD = 4.5 to 6.0 V fX = 6.0 MHz
fX = 4.19 MHz
fX = 6.0 MHz
VDD = 4.5 to 6.0 V
ns
ns
RL = 1 kΩ,
VDD = 4.5 to 6.0 V
ns
CL = 100 pF ^Note
Note RL and CL are the resistance and capacitance of the SO output line load respectively.
(b) Two-wire and three-wire serial I/O modes (SCK ... External clock input):
Parameter
SCK cycle time
SCK high/low level
width
SI setup time
(referred to SCK↑)
SI hold time
(referred to SCK↑)
SCK↓ → SO output
delay time
Symbol
tKCY2
tKL2
tKH2
tSIK2
Min.
800
3200
400
1600
100
tKSI2
400
tKSO2
Typ.
Max.
300
1000
Unit
ns
ns
ns
ns
ns
Conditions
VDD = 4.5 to 6.0 V
VDD = 4.5 to 6.0 V
ns
ns
RL = 1 kΩ,
VDD = 4.5 to 6.0 V
ns
CL = 100 pF ^Note
Note RL and CL are the resistance and capacitance of the SO output line load respectively.
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