UPD78320 Datasheet, PDF (63/88 Pages) NEC – 16/8-BIT SINGLE-CHIP MICROCONTROLLER

µPD78320, 78322
Mnemonic
Operand
CMPBKC
[DE + ], [HL + ]
[DE – ], [HL – ]
[DE + ], A
CMPMNC
[DE – ], A
[DE + ], [HL + ]
CMPBKNC
[DE – ], [HL – ]
MOV
SWRS
SEL
NOP
EI
DI
STBC, #byte
WDM, #byte
RBn
RBn, ALT
Operation
(DE + ) – (HL + ), C ← C–1
2
End if C=0 or CY=0
(DE – ) – (HL – ), C ← C–1
2
End if C=0 or CY=0
(DE + ) – A, C ← C–1
2
End if C=0 or CY=1
(DE – ) – A, C ← C–1
2
End if C=0 or CY=1
(DE + ) – (HL + ), C ← C–1
2
End if C=0 or CY=1
(DE – ) – (HL – ), C ← C–1
2
End if C=0 or CY=1
4 STBC ← byte^Note
4 WDM ← byte^Note
1 RSS ← RSS
2 RBS2–0 ← n, RSS ← 0
2 RBS2–0 ← n, RSS ← 1
1 No Operation
1 IE ← 1 (Enable Interrupt)
1 IE ← 0 (Disable Interrupt)
Flags
S Z AC P/V CY
× × ×V×
×××V×
×××V×
×××V×
×××V×
×××V×
Note
If the operation code of STBC register and WDM register manipulation instructions is abnormal, an operation
code trap interrupt is generated.
Operation in the event of trap:
(SP–1)← PSWH, (SP–2) ← PSWL,
(SP–3)← (PC–4)H, (SP–4) ← (PC–4)L,
PCL ← (003CH), PCH ← (003DH),
SP ← SP–4, IE ← 0
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