MC-45D32CC721 Datasheet, PDF (6/16 Pages) NEC – 32 M-WORD BY 72-BIT DDR SYNCHRONOUS DYNAMIC RAM MODULE UNBUFFERED TYPE

MC-45D32CC721
DC Characteristics 1 (Recommended Operating Conditions unless otherwise noted)
Parameter
Operating current
(ACT-PRE)
Symbol
Test condition
/CAS Grade
latency
IDD0 tRC = tRC(MIN.), tCK = tCK (MIN.), One bank,
Active-precharge, DQ, DM and DQS
inputs changing twice per clock cycle,
Address and control inputs changing
once per clock cycle
-C75
-C80
MIN.
MAX.
TBD
Unit _Notes
mA
TBD
Operating current
(ACT-READ-PRE)
Precharge power down
standby current
Idle standby current
Active power down
standby current
Active standby current
Operating current
(Burst read)
Operating current
(Burst write)
CBR (auto) refresh current
Self refresh current
IDD1
IDD2P
IDD2N
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
tRC = tRC(MIN.), tCK = tCK (MIN.), One
bank, Active-read-precharge,
IO = 0 mA, Burst length = 2,
Address and control inputs
changing once per clock cycle
CL = 2
CL = 2.5
-C75
-C80
-C75
-C80
CKE ≤ VIL(MAX.), tCK = tCK(MIN.),
All banks idle, Power down mode
CKE ≥ VIH(MIN.), tCK = tCK(MIN.), /CS ≥ VIH(MIN.),
All banks idle, Address and other control inputs
changing once per clock cycle
CKE ≤ VIL(MAX.), tCK = tCK(MIN.), One bank active,
Power down mode
/CS ≥ VIH(MIN.), CKE ≥ VIH(MIN.), tCK = tCK(MIN.), tRC =
tRAS(MAX.), One bank, Active-precharge, DQ, DM
and DQS inputs changing twice per clock
cycle, Address and other control inputs
changing once per clock cycle
tCK = tCK(MIN.), Continuous burst
read, Burst length = 2, IO =
0mA, One bank active,
Address and control inputs
changing once per clock cycle
CL = 2
CL = 2.5
-C75
-C80
-C75
-C80
tCK = tCK(MIN.), Continuous burst
write, Burst length = 2, One
bank active, Address and
control inputs changing once
per clock cycle
CL = 2 -C75
-C80
CL = 2.5 -C75
-C80
tRFC = tRFC(MIN.)
-C75
CKE ≤ 0.2 V
-C80
TBD
TBD
TBD
TBD
TBD
TBD
mA ₁
mA
mA
TBD
mA
TBD
mA
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA ₂
mA ₂
mA
mA
Notes 1. IDD1 depends on output loading and cycle rates. Specified values are obtained with the output open.
2. IDD4R and IDD4W depend on output loading and cycle rates. Specified values are obtained with the output
open.
DC Characteristics 2 (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
Test condition
MIN.
Input leakage current
II(L) VI = 0 to 3.6 V, all other pins not under test = 0 V
TBD
Output leakage current
Output high current
IO(L) DOUT is disabled, VO = 0 to VDDQ + 0.3 V
IOH VOUT = VDDQ − 0.43 V
TBD
TBD
Output low current
IOL VOUT = 0.35 V
TBD
MAX.
TBD
TBD
Unit Notes
µA
µA
mA
mA
6
Preliminary Data Sheet M14900EJ1V0DS00