UPD72852A Datasheet, PDF (40/48 Pages) NEC – IEEE1394a-2000 COMPLIANT 400 Mbps TWO-PORT PHY LSI

µPD72852A
DC Characteristics
Common
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Supply current
IDD
Note 1
68
mA
Note 2
60
mA
Note 3
41
mA
Note 4
31
mA
Note 5
115
µA
Notes 1. Transmit maximum packet (all ports transmitting maximum size isochronous packet - 4096 bytes, sent on
every isochronous interval, S400, data value of CCCCCCCCH), VDD = 3.3 V, TA = 25°C
2. Repeat typical packet (receiving on one port DV packets on every isochronous interval, S100, and
transmitting on the other port), VDD = 3.3 V, TA = 25°C
3. Idle (one port receiving and one port transmitting cycle starts), VDD = 3.3 V, TA = 25°C
4. 1 port receiving cycle start packet only, VDD = 3.3 V, TA = 25°C
5. Suspend mode, VDD = 3.3 V, TA = 25°C
PHY/Link Interface
Parameter
High-level output voltage
Low-level output voltage
High-level input voltage
Low-level input voltage
High-level input voltage (schmitt)
Low-level input voltage (schmitt)
High-level input current
Low-level input current
Symbol
Condition
MIN.
TYP.
MAX.
Unit
VOH
CTL0, CTL1, D0-D7, LKON, SCLK, VDD–0.45
V
IOH = –9 mA, VDD > 3 V
CTL0, CTL1, D0-D7, LKON, SCLK,
VDD–0.4
V
IOH = –4 mA, VDD = 2.7 V
VOL
CTL0, CTL1, D0-D7, LKON, SCLK,
IOH = +9 mA, VDD > 3 V
0.4
V
CTL0, CTL1, D0-D7, LKON, SCLK,
IOH = +4 mA, VDD = 2.7 V
0.4
V
VIH
LPS, SPD, DIRECT, PC0-PC2, SUS/RES, 0.7VDD
V
CMC
VIL
LPS, SPD, DIRECT, PC0-PC2, SUS/RES,
CMC
0.2VDD
V
VIHS
CTL0, CTL1, D0-D7, LREQ,
VDD > 3 V
0.456VDD
+0.3
0.456VDD
V
+0.9
VILS
CTL0, CTL1, D0-D7, LREQ,
VDD > 3 V
IIH
CTL0, CTL1, D0-D7,
VI = VDD, DIRECT = 0 V
0.456VDD
–0.9
–10
0.456VDD
V
–0.3
µA
LPS, SPD, DIRECT, PC0-PC2, SUS/RES, –10
CMC,
VI = VDD
IIL
CTL0, CTL1, D0-D7, LKON, SCLK,
VI = 0 V, DIRECT = 0 V
µA
10
µA
LPS, SPD, DIRECT, PC0-PC2, SUS/RES,
CMC,
VI = 0 V
10
µA
40
Data Sheet S16725EJ2V0DS