UPD72852A Datasheet, PDF (25/48 Pages) NEC – IEEE1394a-2000 COMPLIANT 400 Mbps TWO-PORT PHY LSI

(1) LREQ format
• Bus Request
Bit
0
1-3
Type
start
request
4-6
speed
7
stop
Table 4-5. Bus Request Format
Content
Signal that starts a request : 1
Bus request type:
000: ImmReq acknowledge packet transmit
001: IsoReq isochronous packet transmit
010: PriReq cycle start packet transmit
011: FairReq asynchronous packet transmit
Transmit speed:
000: 100 Mbps
010: 200 Mbps
100: 400 Mbps
other: reserved
End request signal : 0 (optional)
• PHY Register Read Request
Table 4-6. Read Request Register Format
Bit
0
1-3
4-7
8
Type
start
request
access address
stop
Signal that starts a request : 1
Read Request.
100 : ReadReq
PHY register address.
End request signal : 0
Content
• PHY Register Write Request
Table 4-7. Write Request Register Format
Bit
0
1-3
4-7
8-15
16
Type
start
request
access address
write data
stop
Signal that starts a request : 1
Write Request.
101 : WriteReq
PHY register address.
Write data.
End request signal : 0
Content
µPD72852A
Data Sheet S16725EJ2V0DS
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