UPD72852A Datasheet, PDF (33/48 Pages) NEC – IEEE1394a-2000 COMPLIANT 400 Mbps TWO-PORT PHY LSI

µPD72852A
Figure 4-7. Link Cancel Timing (After Hold)
PHY CTL0,CTL1
00 11 00 ZZ ZZ
PHY D0-D7
00 00 00 ZZ ZZ
ZZ ZZ ZZ 00
ZZ ZZ ZZ 00
Link CTL0,CTL1
ZZ ZZ ZZ 00 01
01 00 00 ZZ
Link D0-D7
ZZ ZZ ZZ 00 00
00 00 00 ZZ
4.8 Receive
This section shows the operation when the packet is received from the serial bus.
• When the µPD72852A detects DATA_PREFIX on the serial bus, it asserts receive to CTL and all of the D pins
assume the logic value of 1.
• The µPD72852A shows the speed code of the transfer rate ahead of the packet using bits D0-D7. Transmitting
the speed code with the speed signal is the protocol of the PHY/Link interface. The speed code is not included in
the CRC calculation.
• The µPD72852A continues to assert Receive to CTL until the packet is finally transmitted.
• Idle is asserted to CTL, indicating completion of the packet transmission.
PHY CTL0,CTL1
(Binary)
PHY D0-D7
(Hex)
Figure 4-8. Receive Timing
00 10
00 FF
10 10 10 10
FF SP D0 D1
10 00 00
Dn 00 00
The packet transfer rate of the serial bus depends on the topology of the bus. The µPD72852A checks if the node
can receive at the faster transfer rate. At this time, DATA_PREFIX → DATA_END is transmitted to the µPD72852A.
After DATA_PREFIX is transmitted to the Link, Receive from the serial bus is completed, asserting Idle.
Table 4-14 shows the speed code encoding.
Transmitted
00000000
01000000
01010000
11111111
Table 4-14. Speed Encoding
D0-D7
Observed
00xxxxxx
0100xxxx
01010000
11xxxxxx
Data rate
S100
S200
S400
Data Prefix
Data Sheet S16725EJ2V0DS
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