DRV8809 Datasheet, PDF (9/44 Pages) Texas Instruments – COMBINATION MOTOR DRIVERS WITH DC-DC CONVERTERS

DRV8809
DRV8810
www.ti.com ............................................................................................................................................................... SLVS854A – JULY 2008 – REVISED JULY 2008
ELECTRICAL CHARACTERISTICS (continued)
T_J = 0°C to 120°C, V_M = 7 V to 40 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Three DC-DC Converter Protection
I_{O DD ODx}
Overcurrent detect for OD_x
source
Peak current in each ON cycle
tFILT_OCP
t_ODSD
OCP filtering time
DC-DC shutdown filter
By OSCi cycles
Number of subsequent chopping cycles
with OCP detection
Vovpx
Overvoltage protection (OVP)
Percentage of nominal Voutx detected at
VFB
Vuvpx
Undervoltage protection (UVP)
Percentage of nominal Voutx detected at
VFB (VFB decreasing)
tVfilter
OVP/UVP filtering time
t_sst
Start-up time with soft start
V_stover
Start-up overshoot
V_M Supervisory
VthV_M–
nORT for V_M low threshold
VthV_M+
nORT for V_M high threshold
VthV_Mh
VthV_M2
nORT for V_M detect hysteresis
For motor driver off ⁽⁵⁾
t_VM filt
V_M monitor filtering time
Thermal Shutdown (TSD)
Ratio to V_O
V_M decreasing
V_M increasing
(VthV_M+) - (VthV_—)
For V_M threshold detect
T_TSD
Thermal shutdown set points
Temperature Sense, Pre TSD (See Extended Setup Register Definition)
T_TSD0
Temperature sense point 0
Register selectable,
Assert logic H at TH_OUT
T_TSD1
Temperature sense point 1
Register selectable,
Assert logic H at TH_OUT
Tc_sens
TH_OUT (analog out)
temperature coefficient
Specified by design
RESET/nORT: Open-Drain Outputs (nORT, LOGIC_OUT, TH_OUT)
V_OH
High-state voltage
V_OL
Low-state voltage
I_OL
Low-state sink current
t_r
Rise time
t_f
Fall time
RESET/nORT Delay: Start-Up Sequence
R_L = 1 kΩ to 3.3 V
R_L = 1 kΩ to 3.3 V
V_O = 0.4 V
10% to 90%
90% to 10%
t_ord1
nORT delay 1
Reset deassertion from VthV_M+ < VDIN for
DC-DC wake up falling
t_ord3
DC-DC turnon delay
From one DC-DC wake up to following
DC-DC to go soft-start sequence
t_ord4
nORT delay 4
Reset deassertion from 2nd DC-DC wake
up
In-Reset
t_reset
In-Reset assertion to nORT
assertion delay
In-Reset falling to nORT failing
(5) No nORT assertion to VthV_M2 detection
MIN TYP
MAX UNIT
1.8
2
4
25
30
-25 -30
3
8
4.5
5
5.5
6
0.5
1
10
150 170
3A
cycles
chop
cycles
35 %
-35 %
13 us
56 ms
3%
6V
7V
V
15 V
30 µs
190 °C
130 150
120 140
6
170 °C
160 °C
mV/°C
3
V
0.3 V
3
mA
1 µs
50 ns
300
390 ms
1.7
ms
120
180 ms
5
10 µs
Copyright © 2008, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Link(s): DRV8809 DRV8810