N08L083WC2C Datasheet, PDF (4/9 Pages) NanoAmp Solutions, Inc. – 8Mb Ultra-Low Power Asynchronous CMOS SRAM 1024K × 8 bit

NanoAmp Solutions, Inc.
N08L083WC2C
Advance Information
Timing Test Conditions
Item
Input Pulse Level
Input Rise and Fall Time
Input and Output Timing Reference Levels
Output Load
Operating Temperature
0.1V_CC to 0.9 V_CC
1V/ns
0.5 V_CC
CL = 30pF/50pF
-40 to +85 ^oC
Timing
Item
Read Cycle Time
Address Access Time (Random Access)
Chip Enable to Valid Output
Output Enable to Valid Output
Chip Enable to Low-Z output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Symbol
t_RC
t_AA
t_CO
t_OE
t_LZ
t_OLZ
t_HZ
t_OHZ
t_OH
55
Min
Max
55
55
55
25
10
5
20
20
10
Write Cycle Time
Chip Enable to End of Write
Address Valid to End of Write
Write Pulse Width
Address Setup Time
Write Recovery Time
Write to High-Z Output
Data to Write Time Overlap
Data Hold from Write Time
End Write to Low-Z Output
t_WC
55
t_CW
40
t_AW
40
t_WP
40
t_AS
0
t_WR
0
t_WHZ
20
t_DW
25
t_DH
0
t_OW
10
Note:
1. Full device AC operation assumes a 100us ramp time from 0 to Vcc(min) and 200µs wait time after Vcc stablization.
2. Full device operation requires linear Vcc ramp from V_DR to Vcc(min) ≥ 100us or stable at Vcc(min) ≥ 100µs.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Stock No. 23379-A
4
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.