LSN2-T Datasheet, PDF (9/17 Pages) Murata Manufacturing Co., Ltd. – DOSA-SIP, 30A POL DC/DC Converters

LSN2-T/30-D12 Series
DOSA-SIP, 30A POL DC/DC Converters
+VIN
Q1
UP/DN
–VIN
R1
SEQ/TRK
C1
POL A
+VOUT = 5V
that the sequencing controller itself must be “already running” and stabilized
+VIN
R1
MAIN
RAMP
RATE
C1
SEQ/TRK
–VIN
POL A
+VOUT = 5V
R2
SEQ/TRK
R3
C2
POL B
+VOUT = 3.3V
–VIN
ANTI-NOISE FILTER, 1000pF TYP.
before starting up other circuits. If there is a glitch in the system, the power
+VIN
FEEDBACK
TRIM
PWM
CONTROLLER
+VIN
1MΩ
–
+
+VOUT
SEQ/
TRK
IN
Lastly, changing the timing may require reprogramming the logic sequencer or
rewriting software.
Sequence/Track Input
A different power sequencing solution is employed on the LSN2-T/30-D12 DC/DC
converter. After external input power is applied and the converter stabilizes, a
high impedance Sequence/Track input pin accepts an external analog voltage.
The output power voltage will then track this Sequence/Track input at a one-to-
one ratio up to the nominal set point voltage for that converter. This Sequenc-
ing input may be ramped, delayed, stepped or otherwise phased as needed for
the output power, all fully controlled by the user’s simple external circuits. As a
direct input to the converter’s feedback loop, response to the Sequence/Track
input is very fast (milliseconds).
By properly controlling this Sequence pin, most operations of the discrete
On/Off logic sequencer may be duplicated. The Sequence pin system does not
use the converter’s Enable On/Off control (unless it is a master emergency shut
down system).
Power Phasing Architectures
Observe the simplified timing diagrams in this section. There are many pos-
sible power phasing architectures and these are just some examples to help
you analyze your system. Each application will be different. Multiple output
voltages may require more complex timing than that shown here.
These diagrams illustrate the time and slew rate relationship between two
typical power output voltages. Generally the Master will be a primary power
voltage in the system which must be present first or coincident with any
Slave power voltages. The Master output voltage is connected to the Slave’s
Sequence input, either by a voltage divider, divider-plus-capacitor or some
other method.
Several standard sequencing architectures are prevalent. They are con-
cerned with three factors:
■ _{The time relationship between the Master and Slave voltages}
■ _{The voltage difference relationship between the Master and Slave.}
■ _{The voltage slew rate (ramp slope) of each converter’s output.}
For most systems, the time relationship is the dominant factor. The voltage
difference relationship is important for systems very concerned about possible
latchup of programmable devices or overdriving ESD diodes. Lower slew rates
avoid overcurrent shutdown during bypass cap charge-up.
In Figure 10, two POLs ramp up at the same rate until they reach their
different respective final set point voltages. During the ramp, their voltages
are nearly identical. This avoids problems with large currents flowing between
logic systems which are not initialized yet. Since both end voltages are differ-
ent, each converter reaches it’s setpoint voltage at a different time.
up/down sequencer could get out of step with possible disastrous results.
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MDC_LSN2-T/30-D12 Series.B15  Page 9 of 17