LSN2-T Datasheet, PDF (8/17 Pages) Murata Manufacturing Co., Ltd. – DOSA-SIP, 30A POL DC/DC Converters

LSN2-T/30-D12 Series
DOSA-SIP, 30A POL DC/DC Converters
OUTPUT
VOLTAGE
OUTPUT
VOLTAGE
POL A VOUT
POL B VOUT
POL A VOUT
POL B VOUT
Staggered
Times
+VOUT
TIME
Delayed
VOUT Times
TIME
stable and ready to go to work. For additional safety, the sequencer can moni-
tor the output voltages of all downstream POLs with an A/D converter system.
Figure 7. Proportional or Ratiometric Phasing (Identical VOUT Time)
Figure 7 shows two POLs with different slew rates in order to reach differing
final voltages at about the same time.
However, the sequencer controller has some obvious difficulties besides
extra cost, wiring and programming complexity. First, power is applied as a
OUTPUT
VOLTAGE
POL A VOUT
Figure 13. Sequence/Track Simplified Equivalent Schematic
OUTPUT
VOLTAGE
Not Drawn To Scale
POL A VOUT
POL B VOUT
Delayed
VOUT Times
TIME
POL B VOUT
If the power up/down timing needs to be closely controlled, each POL must
be characterized for start-up and down times. These often vary—one POL may
Coincident
VOUT Times
TIME
fast-rising all-or-nothing step which may be unacceptable to certain circuits,
especially large output bypass capacitors. These could force POLs into overcur-
rent shutdown. And some circuits (such as many linear regulators and some
POLs) may not have convenient start-up controls. This requires designing and
fabricating external power controls such as high-current MOSFETs.
Figure 8. Staggered or Sequential Phasing—Inclusive (Fixed Delays)
Figure 9. Staggered or Sequential Phasing—Exclusive
(Fixed Cascaded Delays)
Figure 10. Wiring for Simultaneous Phasing
Figure 11. Self-Ramping Power Up
Figure 12. Proportional Phasing
+VIN
R1
SEQ/TRK
C1
–VIN
POL A
SEQ/TRK
POL B
+VOUT = 5V
+VOUT = 3.3V
stabilize in 15 milliseconds whereas another takes 50 mS. Another problem is
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MDC_LSN2-T/30-D12 Series.B15  Page 8 of 17