LSN2-T Datasheet, PDF (7/17 Pages) Murata Manufacturing Co., Ltd. – DOSA-SIP, 30A POL DC/DC Converters

LSN2-T/30-D12 Series
DOSA-SIP, 30A POL DC/DC Converters
following external factors:
1 – Low initial input line voltage and/or poor regulation of the input source.
2 – Full output load current on lower output voltage converters.
3 – Slow slew rate of input voltage.
4 – Longer distance to input voltage source and/or higher external input
source impedance.
5 – Limited or insufficient ground plane. External wiring that is too small.
6 – Too small external input capacitance. Too high ESR.
7 – High output capacitance causing a start up charge overcurrent surge.
8 – Output loads with excessive inductive reactance or constant current
characteristics.
If the input voltage is already at the low limit before power is applied, the
start up surge current may instantaneously reduce the voltage at the input
terminals to below the specified minimum voltage. Even if this voltage depres-
sion is very brief, this may interfere with the on-board controller and possibly
cause a failed start. Or the converter may start but the input current load will
now drive the input voltage below its running low limit and the converter will
shut down.
If you measure the input voltage before start up with a Digital Voltmeter (DVM),
the voltage may appear to be adequate. Limited external capacitance and/or
too high a source impedance may cause a short downward spike at power up,
causing an instantaneous voltage drop. Use an oscilloscope not a DVM to observe
this spike. The converter’s soft-start controller is sensitive to input voltage. What
matters here is the actual voltage at the input terminals at all times.
Another goal for staggered power-up is to avoid an oversize load applied to
the master source all at once. A more serious reason to manage the timing and
voltage differences is to avoid either a latchup condition in programmable logic
(a latchup might ignore commands or would respond improperly to them) or a
high current startup situation (which may damage on-board circuits). And on
the power down phase, inappropriate timing or voltages can cause interface
logic to send a wrong “epitaph” command (Figure 5).
Figure 5. Power Up/Down Sequencing Controller
Two Approaches
There are two ways to manage these timing and voltage differences. Either the
power up/down sequence can be controlled by discrete On/Off logic controls
for each power supply (see Figure 5). Or the power up/down cycle is set by
Sequencing or Tracking circuits. Some systems combine both methods.
+48V
BUS
CONVERTER
+12Vdc
“ALL ON”
CPU
SEQUENCING
CONTROLLER
+VIN
ENABLE
POL
A
+VIN
ENABLE
POL
B
+5V
LOADS
+3.3V
LOADS
Symptoms of start-up difficulties may include failed started, output oscilla-
tion or brief start up then overcurrent shutdown. Since the input voltage is never
absolutely constant, the converter may start up at some times and not at others.
LSN2-T/30-D12 Power Sequencing
In older systems, one master switch simultaneously turned on the power for all
parts of an application. Many modern systems require multiple supply voltages
for different on-board sections. Typically the CPU or microcontroller needs
1.8 Volts or lower. Memory (particularly DDR) may use 1.8 to 2.5 Volts. Inter-
face “glue” and “chipset” logic might use +3.3Vdc power while Input/Output
subsystems may need +5V. Finally, peripherals use 5V and/or 12V.
TO OTHER POLs
STARTUP SEQUENCE:
ENABLE
ON
POL A
OFF
Settling
Delay
ON
POL B
OFF
Timing is Everything
This mix of system voltages is being distributed by several local power solu-
tions including Intermediate Bus Architecture (IBA) bus converters, Point-of-
load (POL) DC/DC converters and sometimes a linear regulator, all sourced from
a master AC power supply. While this mix of voltages is challenging enough,
a further difficulty is the start-up and shutdown timing relationship between
these power sources and relative voltage differences between them.
For many systems, the CPU and memory must be powered up, boot-strap
loaded and stabilized before the I/O section is turned on. This avoids uncom-
manded data bytes being transferred, compromising an already-running
external network or placing the I/O section in an undefined mode. Or it keeps
bad commands out of disk and peripheral controllers until they are ready to go
to work.
TIME
Figure 6. Coincident or Simultaneous Phasing (Identical Slew Rates)
The first system (discrete On/Off controls) applies signals from an already-
powered logic sequencer or dedicated microcontroller which turns on each
downstream power section in cascaded series. This of course assumes all
POLs have On/Off controls. A distinct advantage of the sequencing controller
is that it can produce an “All On” output signal to state that the full system is
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